PIC24FJ64GA104 FAMILY
25.3.1
WINDOWED OPERATION
25.3.2
CONTROL REGISTER
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDTinstruction
is executed before that window causes a WDT Reset;
this is similar to a WDT time-out.
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The WDT
software option allows the user to enable the WDT for
critical code segments, and disable the WDT during
non-critical segments, for maximum power savings.
Windowed WDT mode is enabled by programming the
WINDIS Configuration bit (CW1<6>) to ‘0’.
FIGURE 25-2:
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN
LPRC Control
Wake From Sleep
FWPSA
WDTPS<3:0>
Prescaler
(5-bit/7-bit)
WDT
Counter
Postscaler
WDT Overflow
1:1 to 1:32.768
LPRC Input
Reset
31 kHz
1 ms/4 ms
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDTInstr.
PWRSAVInstr.
Sleep or Idle Mode
25.4 Deep Sleep Watchdog Timer
(DSWDT)
25.5 Program Verification and
Code Protection
PIC24FJ64GA104 family devices have both a WDT
module and a DSWDT module. The latter runs, if
enabled, when a device is in Deep Sleep and is driven
by either the SOSC or LPRC Oscillator. The clock
source is selected by the DSWDTOSC (CW4<4>)
Configuration bit.
PIC24FJ64GA104 family devices provide two compli-
mentary methods to protect application code from
overwrites and erasures. These also help to protect the
device from inadvertent configuration changes during
run time.
25.5.1
GENERAL SEGMENT PROTECTION
The DSWDT can be configured to generate a time-out
at 2.1 ms to 25.7 days by selecting the respective
postscaler.The postscaler can be selected by the
Configuration bits, DSWDTPS<3:0> (CW4<3:0>).
When the DSWDT is enabled, the clock source is also
enabled. DSWDT is one of the sources that can wake
the device from Deep Sleep mode.
For all devices in the PIC24FJ64GA104 family, the
on-chip program memory space is treated as a single
block, known as the General Segment (GS). Code pro-
tection for this block is controlled by one Configuration
bit, GCP. This bit inhibits external reads and writes to
the program memory space. It has no direct effect in
normal execution mode.
Write protection is controlled by the GWRP bit in the
Configuration Word. When GWRP is programmed to
‘0’, internal write and erase operations to program
memory are blocked.
DS39951C-page 248
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
