PIC18F4580-I/PT 参数 Datasheet PDF下载

型号：	PIC18F4580-I/PT
PDF下载：	下载PDF文件查看货源
内容描述：	28 /40/ 44引脚增强型闪存微控制器与ECAN技术， 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用：	闪存微控制器和处理器外围集成电路时钟
文件页数/大小：	490 页 / 8912 K
品牌：	MICROCHIP [ MICROCHIP ]

PIC18F2480/2580/4480/4580

TABLE 5-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

MCLR Resets,

WDT Reset,

Power-on Reset,

Brown-out Reset

Wake-up via WDT

or Interrupt

Applicable Devices

RESETInstruction,

Stack Resets

B0EIDL⁽⁶⁾

B0EIDH⁽⁶⁾

B0SIDL⁽⁶⁾

B0SIDH⁽⁶⁾

B0CON⁽⁶⁾

TXBIE⁽⁶⁾

2480 2580 4480 4580

xxxx xxxx

xxxx x-xx

xxxx xxxx

0000 0000

---0 00--

0000 0000

0000 00--

0000 0000

0000 0101

0101 0000

---0 0000

0000 0000

0001 0001

0000 0000

xxxx xxxx

xxx- x-xx

xxxx xxxx

xxx- x-xx

xxxx xxxx

uuuu uuuu

uuuu u-uu

uuuu uuuu

0000 0000

---u uu--

0000 0000

0000 00--

0000 0000

0000 0101

0101 0000

---0 0000

0000 0000

0001 0001

0000 0000

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuuu u-uu

uuuu uuuu

---u uu--

uuuu uuuu

uuuu uu--

uuuu uuuu

-u-- uuuu

uuuu uuuu

uuu- u-uu

uuuu uuuu

uuu- u-uu

uuuu uuuu

BIE0⁽⁶⁾

BSEL0⁽⁶⁾

MSEL3⁽⁶⁾

MSEL2⁽⁶⁾

MSEL1⁽⁶⁾

MSEL0⁽⁶⁾

SDFLC⁽⁶⁾

RXFCON1⁽⁶⁾

RXFCON0⁽⁶⁾

RXFBCON7⁽⁶⁾2480 2580 4480 4580

RXFBCON6⁽⁶⁾2480 2580 4480 4580

RXFBCON5⁽⁶⁾2480 2580 4480 4580

RXFBCON4⁽⁶⁾2480 2580 4480 4580

RXFBCON3⁽⁶⁾2480 2580 4480 4580

RXFBCON2⁽⁶⁾2480 2580 4480 4580

RXFBCON1⁽⁶⁾2480 2580 4480 4580

RXFBCON0⁽⁶⁾2480 2580 4480 4580

RXF15EIDL⁽⁶⁾2480 2580 4480 4580

RXF15EIDH⁽⁶⁾2480 2580 4480 4580

RXF15SIDL⁽⁶⁾2480 2580 4480 4580

RXF15SIDH⁽⁶⁾2480 2580 4480 4580

RXF14EIDL⁽⁶⁾2480 2580 4480 4580

RXF14EIDH⁽⁶⁾2480 2580 4480 4580

RXF14SIDL⁽⁶⁾2480 2580 4480 4580

RXF14SIDH⁽⁶⁾2480 2580 4480 4580

Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

4: See Table 5-3 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

DS39637D-page 65

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