PIC18F2480/2580/4480/4580
RETFIE
Return from Interrupt
RETLW
Return Literal to W
Syntax:
RETFIE {s}
Syntax:
RETLW k
Operands:
Operation:
s ∈ [0,1]
Operands:
Operation:
0 ≤ k ≤ 255
(TOS) → PC,
k → W,
1 → GIE/GIEH or PEIE/GIEL;
if s = 1,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
Status Affected:
Encoding:
None
0000
1100
kkkk
kkkk
PCLATU, PCLATH are unchanged.
Description:
W is loaded with the eight-bit literal ‘k’.
The program counter is loaded from the
top of the stack (the return address).
The high address latch (PCLATH)
remains unchanged.
Status Affected:
Encoding:
GIE/GIEH, PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from interrupt. Stack is popped
and Top-of-Stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high or low-priority
global interrupt enable bit. If ‘s’ = 1, the
contents of the shadow registers, WS,
STATUSS and BSRS, are loaded into
their corresponding registers, W,
STATUS and BSR. If ‘s’ = 0, no update
of these registers occurs.
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ‘k’
Process
Data
POP PC
from stack,
Write to W
No
operation
No
operation
No
operation
No
operation
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Example:
Q2
Q3
Q4
CALL TABLE
; W contains table
; offset value
; W now has
Decode
No
operation
No
operation
POP PC
from stack
; table value
Set GIEH or
GIEL
:
TABLE
No
No
No
No
operation
ADDWF PCL
RETLW k0
RETLW k1
:
; W = offset
; Begin table
;
operation
operation
operation
Example:
RETFIE
1
:
After Interrupt
RETLW kn
; End of table
PC
=
=
=
=
=
TOS
WS
W
Before Instruction
BSR
STATUS
GIE/GIEH, PEIE/GIEL
BSRS
W
=
07h
STATUSS
1
After Instruction
W
=
value of kn
DS39637D-page 398
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
