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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
4.1.1  
CLOCK SOURCES  
4.0  
POWER-MANAGED MODES  
The SCS<1:0> bits allow the selection of one of three  
clock sources for power-managed modes. They are:  
PIC18F2480/2580/4480/4580 devices offer a total of  
seven operating modes for more efficient power  
management. These modes provide a variety of  
options for selective power conservation in applications  
where resources may be limited (i.e., battery-powered  
devices).  
• The primary clock, as defined by the FOSC<3:0>  
Configuration bits  
• The secondary clock (the Timer1 oscillator)  
• The internal oscillator block (for RC modes)  
There are three categories of power-managed modes:  
4.1.2  
ENTERING POWER-MANAGED  
MODES  
• Run modes  
• Idle modes  
• Sleep mode  
Switching from one power-managed mode to another  
begins by loading the OSCCON register. The  
SCS<1:0> bits select the clock source and determine  
which Run or Idle mode is to be used. Changing these  
bits causes an immediate switch to the new clock  
source, assuming that it is running. The switch may  
also be subject to clock transition delays. These are  
discussed in Section 4.1.3 “Clock Transitions and  
Status Indicators” and subsequent sections.  
These categories define which portions of the device  
are clocked, and sometimes, what speed. The Run and  
Idle modes may use any of the three available clock  
sources (primary, secondary or internal oscillator  
block); the Sleep mode does not use a clock source.  
The power-managed modes include several  
power-saving features offered on previous PIC®  
devices. One is the clock switching feature, offered in  
other PIC18 devices, allowing the controller to use the  
Timer1 oscillator in place of the primary oscillator. Also  
included is the Sleep mode, offered by all PIC devices,  
where all device clocks are stopped.  
Entry to the power-managed Idle or Sleep modes is  
triggered by the execution of a SLEEPinstruction. The  
actual mode that results depends on the status of the  
IDLEN bit.  
Depending on the current mode and the mode being  
switched to, a change to a power-managed mode does  
not always require setting all of these bits. Many  
transitions may be done by changing the oscillator  
select bits, or changing the IDLEN bit, prior to issuing a  
SLEEP instruction. If the IDLEN bit is already  
configured correctly, it may only be necessary to  
perform a SLEEP instruction to switch to the desired  
mode.  
4.1  
Selecting Power-Managed Modes  
Selecting  
a power-managed mode requires two  
decisions: if the CPU is to be clocked or not and the  
selection of clock source. The IDLEN bit  
(OSCCON<7>) controls CPU clocking, while the  
SCS<1:0> bits (OSCCON<1:0>) select the clock  
source. The individual modes, bit settings, clock sources  
and affected modules are summarized in Table 4-1.  
a
TABLE 4-1:  
Mode  
POWER-MANAGED MODES  
OSCCON<7,1:0> Module Clocking  
IDLEN(1)  
SCS<1:0> CPU Peripherals  
Off Off  
Available Clock and Oscillator Source  
Sleep  
0
N/A  
None – All clocks are disabled  
PRI_RUN  
N/A  
00  
Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(2)  
:
This is the normal full-power execution mode.  
SEC_RUN  
RC_RUN  
PRI_IDLE  
SEC_IDLE  
RC_IDLE  
N/A  
N/A  
1
01  
1x  
00  
01  
1x  
Clocked Clocked Secondary – Timer1 Oscillator  
Clocked Clocked Internal Oscillator Block(2)  
Off  
Off  
Off  
Clocked Primary – LP, XT, HS, HSPLL, RC, EC  
Clocked Secondary – Timer1 Oscillator  
Clocked Internal Oscillator Block(2)  
1
1
Note 1: IDLEN reflects its value when the SLEEPinstruction is executed.  
2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.  
© 2009 Microchip Technology Inc.  
DS39637D-page 39  
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