PIC18F2480/2580/4480/4580
On transitions from SEC_RUN mode to PRI_RUN
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock is providing the clock. The IDLEN and
SCS bits are not affected by the wake-up; the Timer1
oscillator continues to run.
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1
Q2
Q3
Q4
Q1
Q2
Q3
1
2
3
n-1
n
T1OSI
OSC1
Clock Transition
CPU
Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
PC + 4
FIGURE 4-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
(1)
TOST
(1)
TPLL
1
2
n-1 n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC + 2
PC + 4
PC
OSTS Bit Set
SCS<1:0> Bits Changed
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
the INTOSC multiplexer (see Figure 4-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides the
best power conservation of all the Run modes, while
still executing code. It works well for user applications
which are not highly timing-sensitive or do not require
high-speed clocks at all times.
Note:
Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable differences between PRI_RUN and
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to, and exit from,
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
© 2009 Microchip Technology Inc.
DS39637D-page 41
MICROCHIP [ MICROCHIP ]
