欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4580-I/PT的Datasheet PDF文件第31页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第32页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第33页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第34页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第36页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第37页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第38页浏览型号PIC18F4580-I/PT的Datasheet PDF文件第39页  
PIC18F2480/2580/4480/4580  
The IDLEN bit determines if the device goes into Sleep  
mode or one of the Idle modes when the SLEEP  
instruction is executed.  
3.7.1  
OSCILLATOR CONTROL REGISTER  
The OSCCON register (Register 3-2) controls several  
aspects of the device clock’s operation, both in  
full-power operation and in power-managed modes.  
The use of the flag and control bits in the OSCCON  
register is discussed in more detail in Section 4.0  
“Power-Managed Modes”.  
The System Clock Select bits, SCS<1:0>, select the  
clock source. The available clock sources are the  
primary clock (defined by the FOSC<3:0> Configura-  
tion bits), the secondary clock (Timer1 oscillator) and  
the internal oscillator block. The clock source changes  
immediately after one or more of the bits is written to,  
following a brief clock transition interval. The SCS bits  
are cleared on all forms of Reset.  
Note 1: The Timer1 oscillator must be enabled to  
select the secondary clock source. The  
Timer1 oscillator is enabled by setting the  
T1OSCEN bit in the Timer1 Control regis-  
ter (T1CON<3>). If the Timer1 oscillator is  
not enabled, then any attempt to select a  
secondary clock source when executing a  
SLEEPinstruction will be ignored.  
The Internal Oscillator Frequency Select bits,  
IRCF<2:0>, select the frequency output of the internal  
oscillator block to drive the device clock. The choices  
are the INTRC source, the INTOSC source (8 MHz) or  
one of the frequencies derived from the INTOSC post-  
scaler (31 kHz to 4 MHz). If the internal oscillator block  
is supplying the device clock, changing the states of  
these bits will have an immediate change on the inter-  
nal oscillator’s output. On device Resets, the default  
output frequency of the internal oscillator block is set at  
1 MHz.  
2: It is recommended that the Timer1  
oscillator be operating and stable before  
executing the SLEEPinstruction, or a very  
long delay may occur while the Timer1  
oscillator starts.  
3.7.2  
OSCILLATOR TRANSITIONS  
PIC18F2480/2580/4480/4580 devices contain circuitry  
to prevent clock “glitches” when switching between  
clock sources. A short pause in the device clock occurs  
during the clock switch. The length of this pause is the  
sum of two cycles of the old clock source and three to  
four cycles of the new clock source. This formula  
assumes that the new clock source is stable.  
When an output frequency of 31 kHz is selected  
(IRCF<2:0> = 000), users may choose which internal  
oscillator acts as the source. This is done with the  
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).  
Setting this bit selects INTOSC as a 31.25 kHz clock  
source by enabling the divide-by-256 output of the  
INTOSC postscaler. Clearing INTSRC selects INTRC  
(nominally 31 kHz) as the clock source.  
Clock transitions are discussed in greater detail in  
Section 4.1.2 “Entering Power-Managed Modes”.  
This option allows users to select the tunable and more  
precise INTOSC as a clock source, while maintaining  
power savings with a very low clock speed. Regardless  
of the setting of INTSRC, INTRC always remains the  
clock source for features such as the Watchdog Timer  
and the Fail-Safe Clock Monitor.  
The OSTS, IOFS and T1RUN bits indicate which clock  
source is currently providing the device clock. The  
OSTS bit indicates that the Oscillator Start-up Timer  
(OST) has timed out and the primary clock is providing  
the device clock in primary clock modes. The IOFS bit  
indicates when the internal oscillator block has stabi-  
lized and is providing the device clock in RC Clock  
modes. The T1RUN bit (T1CON<6>) indicates when  
the Timer1 oscillator is providing the device clock in  
secondary clock modes. In power-managed modes,  
only one of these three bits will be set at any time. If  
none of these bits are set, the INTRC is providing the  
clock or the internal oscillator block has just started and  
is not yet stable.  
© 2009 Microchip Technology Inc.  
DS39637D-page 35  
 复制成功!