PIC18F2480/2580/4480/4580
3.4
RC Oscillator
3.5
PLL Frequency Multiplier
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The actual oscillator frequency is a function of several
factors:
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
• supply voltage
• values of the external resistor (REXT) and
capacitor (CEXT)
• operating temperature
3.5.1
HSPLL OSCILLATOR MODE
Given the same device, operating voltage and tempera-
ture and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
• normal manufacturing variation
• difference in lead frame capacitance between
package types (especially for low CEXT values)
The PLL is only available to the crystal oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (= 0110).
• variations within the tolerance of limits of REXT
and CEXT
FIGURE 3-7:
PLL BLOCK DIAGRAM
(HS MODE)
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows how the R/C combination is
connected.
HS Osc Enable
PLL Enable
(from Configuration Register 1H)
FIGURE 3-5:
RC OSCILLATOR MODE
OSC2
Phase
VDD
HS Mode
Crystal
Osc
FIN
Comparator
OSC1
FOUT
REXT
Internal
OSC1
Clock
Loop
Filter
CEXT
VSS
PIC18FXXXX
OSC2/CLKO
÷4
VCO
FOSC/4
SYSCLK
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
The RCIO Oscillator mode (Figure 3-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
3.5.2
PLL AND INTOSC
The PLL is also available to the internal oscillator block
in selected oscillator modes. In this configuration, the
PLL is enabled in software and generates a clock
output of up to 32 MHz. The operation of INTOSC with
the PLL is described in Section 3.6.4 “PLL in INTOSC
Modes”.
FIGURE 3-6:
RCIO OSCILLATOR MODE
VDD
REXT
Internal
OSC1
Clock
CEXT
PIC18FXXXX
VSS
I/O (OSC2)
RA6
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
© 2009 Microchip Technology Inc.
DS39637D-page 31
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