PIC18F2480/2580/4480/4580
TABLE 24-1: CAN CONTROLLER REGISTER MAP
Address(1)
F7Fh
Name
Address
Name
Address
Name
Address
Name
SPBRGH(3)
BAUDCON(3)
F5Fh CANCON_RO0
F5Eh CANSTAT_RO0
F3Fh CANCON_RO2
F3Eh CANSTAT_RO2
F1Fh RXM1EIDL
F1Eh RXM1EIDH
F1Dh RXM1SIDL
F1Ch RXM1SIDH
F1Bh RXM0EIDL
F1Ah RXM0EIDH
F19h RXM0SIDL
F18h RXM0SIDH
F17h RXF5EIDL
F16h RXF5EIDH
F15h RXF5SIDL
F14h RXF5SIDH
F13h RXF4EIDL
F12h RXF4EIDH
F11h RXF4SIDL
F10h RXF4SIDH
F0Fh RXF3EIDL
F0Eh RXF3EIDH
F0Dh RXF3SIDL
F0Ch RXF3SIDH
F0Bh RXF2EIDL
F0Ah RXF2EIDH
F09h RXF2SIDL
F08h RXF2SIDH
F07h RXF1EIDL
F06h RXF1EIDH
F05h RXF1SIDL
F04h RXF1SIDH
F03h RXF0EIDL
F02h RXF0EIDH
F01h RXF0SIDL
F00h RXF0SIDH
F7Eh
(4)
F7Dh
—
F5Dh
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
RXB1D7
RXB1D6
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
TXB1D7
TXB1D6
(4)
F7Ch
—
(4)
F7Bh
—
RXB1D5
TXB1D5
(4)
F7Ah
—
RXB1D4
TXB1D4
F79h ECCP1DEL(3)
RXB1D3
TXB1D3
(4)
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
—
RXB1D2
TXB1D2
ECANCON
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
RXB1D1
TXB1D1
RXB1D0
TXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
TXB1DLC
TXB1EIDL
TXB1EIDH
TXB1SIDL
TXB1SIDH
TXB1CON
BRGCON3
BRGCON2
BRGCON1
CANCON
CANSTAT
RXB0D7
F4Fh CANCON_RO1(2)
F4Eh CANSTAT_RO1(2)
F2Fh CANCON_RO3(2)
F2Eh CANSTAT_RO3(2)
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
TXB0D7
TXB0D6
F2Dh
F2Ch
F2Bh
F2Ah
F29h
F28h
F27h
F26h
F25h
F24h
F23h
F22h
F21h
F20h
TXB2D7
TXB2D6
RXB0D6
RXB0D5
TXB0D5
TXB2D5
RXB0D4
TXB0D4
TXB2D4
RXB0D3
TXB0D3
TXB2D3
RXB0D2
TXB0D2
TXB2D2
RXB0D1
TXB0D1
TXB2D1
RXB0D0
TXB0D0
TXB2D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
TXB0DLC
TXB0EIDL
TXB0EIDH
TXB0SIDL
TXB0SIDH
TXB0CON
TXB2DLC
TXB2EIDL
TXB2EIDH
TXB2SIDL
TXB2SIDH
TXB2CON
Note 1: Shaded registers are available in Access Bank low area, while the rest are available in Bank 15.
2: CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given
for each instance of the controller register due to the Microchip header file requirement.
3: These registers are not CAN registers.
4: Unimplemented registers are read as ‘0’.
© 2009 Microchip Technology Inc.
DS39637D-page 325
MICROCHIP [ MICROCHIP ]
