PIC18F2480/2580/4480/4580
REGISTER 24-3: ECANCON: ENHANCED CAN CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
MDSEL1(1)
MDSEL0(1)
FIFOWM(2)
EWIN4
EWIN3
EWIN2
EWIN1
EWIN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7-6
MDSEL<1:0>: Mode Select bits(1)
00= Legacy mode (Mode 0, default)
01= Enhanced Legacy mode (Mode 1)
10= Enhanced FIFO mode (Mode 2)
11= Reserved
bit 5
FIFOWM: FIFO High Water Mark bit(2)
1= Will cause FIFO interrupt when one receive buffer remains
0= Will cause FIFO interrupt when four receive buffers remain(3)
bit 4-0
EWIN<4:0>: Enhanced Window Address bits
These bits map the group of 16 banked CAN SFRs into Access Bank addresses 0F60-0F6Dh. The
exact group of registers to map is determined by the binary value of these bits.
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
00000= Acceptance Filters 0, 1, 2 and BRGCON2, 3
00001= Acceptance Filters 3, 4, 5 and BRGCON1, CIOCON
00010= Acceptance Filter Masks, Error and Interrupt Control
00011= Transmit Buffer 0
00100= Transmit Buffer 1
00101= Transmit Buffer 2
00110= Acceptance Filters 6, 7, 8
00111= Acceptance Filters 9, 10, 11
01000= Acceptance Filters 12, 13, 14
01001= Acceptance Filters 15
01010-01110= Reserved
01111= RXINT0, RXINT1
10000= Receive Buffer 0
10001= Receive Buffer 1
10010= TX/RX Buffer 0
10011= TX/RX Buffer 1
10100= TX/RX Buffer 2
10101= TX/RX Buffer 3
10110= TX/RX Buffer 4
10111= TX/RX Buffer 5
11000-11111= Reserved
Note 1: These bits can only be changed in Configuration mode. See Register 24-1 to change to Configuration mode.
2: This bit is used in Mode 2 only.
3: If FIFO is configured to contain four or less buffers, then the FIFO interrupt will trigger.
DS39637D-page 286
© 2009 Microchip Technology Inc.
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