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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
24.2.2  
DEDICATED CAN TRANSMIT  
BUFFER REGISTERS  
This section describes the dedicated CAN Transmit  
Buffer registers and their associated control registers.  
REGISTER 24-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 n 2]  
U-0  
R-0  
TXABT(1)  
R-0  
R-0  
R/W-0  
U-0  
R/W-0  
TXPRI1(3) TXPRI0(3)  
R/W-0  
Mode 0  
TXLARB(1) TXERR(1) TXREQ(2)  
R/C-0  
TXBIF  
R-0  
TXABT(1)  
R-0  
R-0  
R/W-0  
U-0  
R/W-0  
TXPRI1(3) TXPRI0(3)  
bit 0  
R/W-0  
Mode 1,2  
TXLARB(1) TXERR(1) TXREQ(2)  
bit 7  
Legend:  
C = Clearable bit  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
Mode 0:  
Unimplemented: Read as ‘0’  
Mode 1, 2:  
TXBIF: Transmit Buffer Interrupt Flag bit  
1= Transmit buffer has completed transmission of message and may be reloaded  
0= Transmit buffer has not completed transmission of a message  
bit 6  
bit 5  
bit 4  
bit 3  
TXABT: Transmission Aborted Status bit(1)  
1= Message was aborted  
0= Message was not aborted  
TXLARB: Transmission Lost Arbitration Status bit(1)  
1= Message lost arbitration while being sent  
0= Message did not lose arbitration while being sent  
TXERR: Transmission Error Detected Status bit(1)  
1= A bus error occurred while the message was being sent  
0= A bus error did not occur while the message was being sent  
TXREQ: Transmit Request Status bit(2)  
1= Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.  
0= Automatically cleared when the message is successfully sent  
bit 2  
Unimplemented: Read as ‘0’  
TXPRI<1:0>: Transmit Priority bits(3)  
bit 1-0  
11= Priority Level 3 (highest priority)  
10= Priority Level 2  
01= Priority Level 1  
00= Priority Level 0 (lowest priority)  
Note 1: This bit is automatically cleared when TXREQ is set.  
2: While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is  
set will request a message abort.  
3: These bits define the order in which transmit buffers will be transferred. They do not alter the CAN  
message identifier.  
DS39637D-page 288  
© 2009 Microchip Technology Inc.  
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