PIC18F2480/2580/4480/4580
18.3.8
OPERATION IN POWER-MANAGED
MODES
18.3.9
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
In SPI Master mode, module clocks may be operating
at a different speed than when in full-power mode; in
the case of the Sleep mode, all clocks are halted.
18.3.10 BUS MODE COMPATIBILITY
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
In most power-managed modes, a clock is provided to
the peripherals. That clock should be from the primary
clock source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See Section 3.7
“Clock Sources and Oscillator Switching” for
additional information.
TABLE 18-1: SPI BUS MODES
Control Bits State
Standard SPI Mode
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
If MSSP interrupts are enabled, they can wake the con-
troller from Sleep mode, or one of the Idle modes, when
the master completes sending data. If an exit from
Sleep or Idle mode is not desired, MSSP interrupts
should be disabled.
There is also a SMP bit which controls when the data is
sampled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the device wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power-managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Reset
Values
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
RBIF
55
58
58
58
58
58
56
56
56
PSPIF(1)
PSPIE(1)
PSPIP(1)
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TMR2IF
TMR1IF
PIE1
TXIE
TXIP
TMR2IE TMR1IE
TMR2IP TMR1IP
IPR1
TRISA
PORTA Data Direction Register
PORTC Data Direction Register
TRISC
SSPBUF
SSPCON1
SSPSTAT
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1
UA
SSPM0
BF
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1: These bits are unimplemented in PIC18F2X80 devices; always maintain these bits clear.
© 2009 Microchip Technology Inc.
DS39637D-page 199
MICROCHIP [ MICROCHIP ]
