PIC18F2480/2580/4480/4580
17.4.4
HALF-BRIDGE MODE
FIGURE 17-4:
HALF-BRIDGE PWM
OUTPUT
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the P1A pin, while the complemen-
tary PWM output signal is output on the P1B pin
(Figure 17-4). This mode can be used for half-bridge
applications, as shown in Figure 17-5, or for full-bridge
applications where four power switches are being
modulated with two PWM signals.
Period
Period
Duty Cycle
(2)
(2)
P1A
td
td
P1B
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits,
PDC<6:0>, sets the number of instruction cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 17.4.6
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
Since the P1A and P1B outputs are multiplexed with
the PORTD<4> and PORTD<5> data latches, the
TRISD<4> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 17-5:
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
PIC18F2X80/4X80
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
Half-Bridge Output Driving a Full-Bridge Circuit
V+
PIC18F2X80/4X80
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
V-
DS39637D-page 182
© 2009 Microchip Technology Inc.
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