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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
17.4.2  
PWM DUTY CYCLE  
EQUATION 17-3:  
The PWM duty cycle is specified by writing to the  
ECCPR1L register and to the ECCP1CON<5:4> bits.  
Up to 10-bit resolution is available. The ECCPR1L  
contains the eight MSbs and the ECCP1CON<5:4> bits  
contain the two LSbs. This 10-bit value is represented  
by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle  
is calculated by the following equation.  
FOSC  
log  
(FPWM)  
bits  
PWM Resolution (max) =  
log(2)  
Note:  
If the PWM duty cycle value is longer than  
the PWM period, the CCP1 pin will not be  
cleared.  
EQUATION 17-2:  
PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> •  
TOSC • (TMR2 Prescale Value)  
17.4.3  
PWM OUTPUT CONFIGURATIONS  
The EPWM1M<1:0> bits in the ECCP1CON register  
allow one of four configurations:  
ECCPR1L and ECCP1CON<5:4> can be written to at  
any time, but the duty cycle value is not copied into  
ECCPR1H until a match between PR2 and TMR2  
occurs (i.e., the period is complete). In PWM mode,  
ECCPR1H is a read-only register.  
• Single Output  
• Half-Bridge Output  
• Full-Bridge Output, Forward mode  
• Full-Bridge Output, Reverse mode  
The ECCPR1H register and a 2-bit internal latch are  
used to double-buffer the PWM duty cycle. This  
double-buffering is essential for glitchless PWM opera-  
tion. When the ECCPR1H and 2-bit latch match TMR2,  
concatenated with an internal 2-bit Q clock or two bits  
of the TMR2 prescaler, the ECCP1 pin is cleared. The  
maximum PWM resolution (bits) for a given PWM  
frequency is given by the following equation.  
The Single Output mode is the standard PWM mode  
discussed in Section 17.4 “Enhanced PWM Mode”.  
The Half-Bridge and Full-Bridge Output modes are  
covered in detail in the sections that follow.  
The general relationship of the outputs in all  
configurations is summarized in Figure 17-2.  
TABLE 17-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz  
PWM Frequency  
2.44 kHz  
9.77 kHz  
39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz  
Timer Prescaler (1, 4, 16)  
PR2 Value  
16  
FFh  
10  
4
1
1
3Fh  
8
1
1Fh  
7
1
FFh  
10  
FFh  
10  
17h  
6.58  
Maximum Resolution (bits)  
DS39637D-page 180  
© 2009 Microchip Technology Inc.  
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