PIC18F2480/2580/4480/4580
17.4.1
PWM PERIOD
17.4 Enhanced PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured by setting the EPWM1M<1:0> and
CCP1M<3:0> bits of the ECCP1CON register.
EQUATION 17-1:
PWM Period = [(PR2) + 1] • 4 • TOSC •
(TMR2 Prescale Value)
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
Figure 17-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to
prevent glitches on any of the outputs. The exception is
the ECCP PWM Dead-Band Delay register,
ECCP1DEL, which is loaded at either the duty cycle
boundary or the boundary period (whichever comes
first). Because of the buffering, the module waits until
the assigned timer resets instead of starting immedi-
ately. This means that Enhanced PWM waveforms do
not exactly match the standard PWM waveforms, but
are instead offset by one full instruction cycle (4 TOSC).
• TMR2 is cleared
• The ECCP1 pin is set (if PWM duty cycle = 0%,
the ECCP1 pin will not be set)
• The PWM duty cycle is copied from ECCPR1L
into ECCPR1H
Note:
The Timer2 postscaler (see Section 14.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 17-1:
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
CCP1CON<5:4>
EPWM1M1<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
ECCPR1L
ECCP1/P1A
ECCP1/P1A
P1B
TRISD<4>
TRISD<5>
TRISD<6>
TRISD<7>
ECCPR1H (Slave)
Comparator
P1B
Output
Controller
R
S
Q
P1C
P1C
P1D
(Note 1)
TMR2
P1D
Comparator
PR2
Clear Timer,
set ECCP1 pin and
latch D.C.
ECCP1DEL
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time
base.
© 2009 Microchip Technology Inc.
DS39637D-page 179
MICROCHIP [ MICROCHIP ]
