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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
12.3.1  
SWITCHING PRESCALER  
ASSIGNMENT  
12.3 Prescaler  
An 8-bit counter is available as a prescaler for the Timer0  
module. The prescaler is not directly readable or writable;  
its value is set by the PSA and T0PS<2:0> bits  
(T0CON<3:0>) which determine the prescaler  
assignment and prescale ratio.  
The prescaler assignment is fully under software  
control and can be changed “on-the-fly” during program  
execution.  
12.4 Timer0 Interrupt  
Clearing the PSA bit assigns the prescaler to the  
Timer0 module. When it is assigned, prescale values  
from 1:2 through 1:256 in power-of-2 increments are  
selectable.  
The TMR0 interrupt is generated when the TMR0  
register overflows from FFh to 00h in 8-bit mode, or  
from FFFFh to 0000h in 16-bit mode. This overflow sets  
the TMR0IF flag bit. The interrupt can be masked by  
clearing the TMR0IE bit (INTCON<5>). Before re-  
enabling the interrupt, the TMR0IF bit must be cleared  
in software by the Interrupt Service Routine.  
When assigned to the Timer0 module, all instructions  
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF  
TMR0, BSF TMR0, etc.) clear the prescaler count.  
Note:  
Writing to TMR0 when the prescaler is  
assigned to Timer0 will clear the prescaler  
count but will not change the prescaler  
assignment.  
Since Timer0 is shut down in Sleep mode, the TMR0  
interrupt cannot awaken the processor from Sleep.  
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0  
Reset  
Values  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
on Page:  
TMR0L  
Timer0 Register Low Byte  
Timer0 Register High Byte  
56  
56  
55  
56  
58  
TMR0H  
INTCON  
T0CON  
TRISA  
GIE/GIEH PEIE/GIEL TMR0IE  
TMR0ON T08BIT T0CS  
TRISA7(1) TRISA6(1) PORTA Data Direction Register  
INT0IE  
T0SE  
RBIE  
PSA  
TMR0IF  
T0PS2  
INT0IF  
T0PS1  
RBIF  
T0PS0  
Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0.  
Note 1: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various  
primary oscillator modes. When disabled, these bits read as ‘0’.  
© 2009 Microchip Technology Inc.  
DS39637D-page 153  
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