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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
REGISTER 2-1:  
OSCTUNE: OSCILLATOR TUNING REGISTER  
R/W-0  
R/W-0(1)  
PLLEN(1)  
U-0  
R/W-0  
TUN4  
R/W-0  
TUN3  
R/W-0  
TUN2  
R/W-0  
TUN1  
R/W-0  
TUN0  
INTSRC  
bit 7  
bit 0  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
-n = Value at POR  
bit 7  
bit 6  
INTSRC: Internal Oscillator Low-Frequency Source Select bit  
1= 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)  
0= 31 kHz device clock derived directly from INTRC internal oscillator  
PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)  
1= PLL enabled for INTOSC (4 MHz and 8 MHz only)  
0= PLL disabled  
bit 5  
Unimplemented: Read as ‘0’  
TUN<4:0>: Frequency Tuning bits  
011111= Maximum frequency  
bit 4-0  
000001  
000000= Center frequency. Oscillator module is running at the calibrated frequency.  
111111  
100000= Minimum frequency  
Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See  
Section 2.6.4 “PLL in INTOSC Modes” for details.  
2.6.5.1  
Compensating with the EUSART  
2.6.5.3  
Compensating with the CCP Module  
in Capture Mode  
An adjustment may be required when the EUSART  
begins to generate framing errors or receives data with  
errors while in Asynchronous mode. Framing errors  
indicate that the device clock frequency is too high. To  
adjust for this, decrement the value in OSCTUNE to  
reduce the clock frequency. On the other hand, errors  
in data may suggest that the clock speed is too low. To  
compensate, increment OSCTUNE to increase the  
clock frequency.  
A CCP module can use free-running Timer1 (or  
Timer3), clocked by the internal oscillator block and an  
external event with a known period (i.e., AC power fre-  
quency). The time of the first event is captured in the  
CCPRxH:CCPRxL registers and is recorded for use  
later. When the second event causes a capture, the  
time of the first event is subtracted from the time of the  
second event. Since the period of the external event is  
known, the time difference between events can be  
calculated.  
2.6.5.2  
Compensating with the Timers  
This technique compares device clock speed to some  
reference clock. Two timers may be used; one timer is  
clocked by the peripheral clock, while the other is  
clocked by a fixed reference source, such as the  
Timer1 oscillator.  
If the measured time is much greater than the calcu-  
lated time, the internal oscillator block is running too  
fast; to compensate, decrement the OSCTUNE register.  
If the measured time is much less than the calculated  
time, the internal oscillator block is running too slow; to  
compensate, increment the OSCTUNE register.  
Both timers are cleared, but the timer clocked by the  
reference generates interrupts. When an interrupt  
occurs, the internally clocked timer is read and both  
timers are cleared. If the internally clocked timer value  
is greater than expected, then the internal oscillator  
block is running too fast. To adjust for this, decrement  
the OSCTUNE register.  
© 2008 Microchip Technology Inc.  
DS39631E-page 27  
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