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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
2.4  
RC Oscillator  
2.5  
PLL Frequency Multiplier  
For timing insensitive applications, the “RC” and  
“RCIO” device options offer additional cost savings.  
The actual oscillator frequency is a function of several  
factors:  
A Phase Locked Loop (PLL) circuit is provided as an  
option for users who wish to use a lower frequency  
oscillator circuit or to clock the device up to its highest  
rated frequency from a crystal oscillator. This may be  
useful for customers who are concerned with EMI due  
to high-frequency crystals or users who require higher  
clock speeds from an internal oscillator.  
• supply voltage  
• values of the external resistor (REXT) and  
capacitor (CEXT)  
• operating temperature  
2.5.1  
HSPLL OSCILLATOR MODE  
Given the same device, operating voltage and tempera-  
ture and component values, there will also be unit-to-unit  
frequency variations. These are due to factors such as:  
The HSPLL mode makes use of the HS Oscillator  
mode for frequencies up to 10 MHz. A PLL then multi-  
plies the oscillator output frequency by 4 to produce an  
internal clock frequency up to 40 MHz. The PLLEN bit  
is not available in this oscillator mode.  
• normal manufacturing variation  
• difference in lead frame capacitance between  
package types (especially for low CEXT values)  
The PLL is only available to the crystal oscillator when  
the FOSC<3:0> Configuration bits are programmed for  
HSPLL mode (= 0110).  
• variations within the tolerance of limits of REXT  
and CEXT  
In the RC Oscillator mode, the oscillator frequency  
divided by 4 is available on the OSC2 pin. This signal  
may be used for test purposes or to synchronize other  
logic. Figure 2-5 shows how the R/C combination is  
connected.  
FIGURE 2-7:  
PLL BLOCK DIAGRAM (HS  
MODE)  
HS Oscillator Enable  
PLL Enable  
(from Configuration Register 1H)  
FIGURE 2-5:  
RC OSCILLATOR MODE  
VDD  
OSC2  
OSC1  
Phase  
Comparator  
HS Mode  
Crystal  
Osc  
FIN  
REXT  
FOUT  
Internal  
OSC1  
Clock  
Loop  
Filter  
CEXT  
VSS  
PIC18FXXXX  
OSC2/CLKO  
FOSC/4  
÷4  
VCO  
SYSCLK  
Recommended values: 3 kΩ ≤ REXT 100 kΩ  
CEXT > 20 pF  
The RCIO Oscillator mode (Figure 2-6) functions like  
the RC mode, except that the OSC2 pin becomes an  
additional general purpose I/O pin. The I/O pin  
becomes bit 6 of PORTA (RA6).  
2.5.2  
PLL AND INTOSC  
The PLL is also available to the internal oscillator block  
in selected oscillator modes. In this configuration, the  
PLL is enabled in software and generates a clock out-  
put of up to 32 MHz. The operation of INTOSC with the  
PLL is described in Section 2.6.4 “PLL in INTOSC  
Modes”.  
FIGURE 2-6:  
RCIO OSCILLATOR MODE  
VDD  
REXT  
Internal  
OSC1  
Clock  
CEXT  
PIC18FXXXX  
VSS  
I/O (OSC2)  
RA6  
Recommended values: 3 kΩ ≤ REXT 100 kΩ  
CEXT > 20 pF  
© 2008 Microchip Technology Inc.  
DS39631E-page 25  
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