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PIC18F4520-I/P 参数 Datasheet PDF下载

PIC18F4520-I/P图片预览
型号: PIC18F4520-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 412 页 / 6898 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2420/2520/4420/4520  
not require a device clock source (i.e., MSSP slave,  
2.8  
Effects of Power-Managed Modes  
on the Various Clock Sources  
PSP, INTx pins and others). Peripherals that may add  
significant current consumption are listed in  
Section 26.2 “DC Characteristics”.  
When PRI_IDLE mode is selected, the designated pri-  
mary oscillator continues to run without interruption.  
For all other power-managed modes, the oscillator  
using the OSC1 pin is disabled. The OSC1 pin (and  
OSC2 pin, if used by the oscillator) will stop oscillating.  
2.9  
Power-up Delays  
Power-up delays are controlled by two timers so that no  
external Reset circuitry is required for most applica-  
tions. The delays ensure that the device is kept in  
Reset until the device power supply is stable under nor-  
mal circumstances and the primary clock is operating  
and stable. For additional information on power-up  
delays, see Section 4.5 “Device Reset Timers”.  
In secondary clock modes (SEC_RUN and  
SEC_IDLE), the Timer1 oscillator is operating and pro-  
viding the device clock. The Timer1 oscillator may also  
run in all power-managed modes if required to clock  
Timer1 or Timer3.  
In internal oscillator modes (RC_RUN and RC_IDLE),  
the internal oscillator block provides the device clock  
source. The 31 kHz INTRC output can be used directly  
to provide the clock and may be enabled to support  
various special features, regardless of the power-  
managed mode (see Section 23.2 “Watchdog Timer  
(WDT)”, Section 23.3 “Two-Speed Start-up” and  
Section 23.4 “Fail-Safe Clock Monitor” for more  
information on WDT, Fail-Safe Clock Monitor and Two-  
Speed Start-up). The INTOSC output at 8 MHz may be  
used directly to clock the device or may be divided  
down by the postscaler. The INTOSC output is disabled  
if the clock is provided directly from the INTRC output.  
The first timer is the Power-up Timer (PWRT), which  
provides a fixed delay on power-up (parameter 33,  
Table 26-10). It is enabled by clearing (= 0) the  
PWRTEN Configuration bit.  
The second timer is the Oscillator Start-up Timer  
(OST), intended to keep the chip in Reset until the  
crystal oscillator is stable (LP, XT and HS modes). The  
OST does this by counting 1024 oscillator cycles  
before allowing the oscillator to clock the device.  
When the HSPLL Oscillator mode is selected, the  
device is kept in Reset for an additional 2 ms, following  
the HS mode OST delay, so the PLL can lock to the  
incoming clock frequency.  
If Sleep mode is selected, all clock sources are  
stopped. Since all the transistor switching currents  
have been stopped, Sleep mode achieves the lowest  
current consumption of the device (only leakage  
currents).  
There is a delay of interval, TCSD (parameter 38,  
Table 26-10), following POR, while the controller  
becomes ready to execute instructions. This delay runs  
concurrently with any other delays. This may be the  
only delay that occurs when any of the EC, RC or INTIO  
modes are used as the primary clock source.  
Enabling any on-chip feature that will operate during  
Sleep will increase the current consumed during Sleep.  
The INTRC is required to support WDT operation. The  
Timer1 oscillator may be operating to support a Real-  
Time Clock. Other features may be operating that do  
TABLE 2-3:  
OSC1 AND OSC2 PIN STATES IN SLEEP MODE  
OSC1 Pin  
OSC Mode  
OSC2 Pin  
RC, INTIO1  
RCIO  
Floating, external resistor should pull high  
Floating, external resistor should pull high  
Configured as PORTA, bit 7  
At logic low (clock/4 output)  
Configured as PORTA, bit 6  
Configured as PORTA, bit 6  
Configured as PORTA, bit 6  
At logic low (clock/4 output)  
INTIO2  
ECIO  
Floating, pulled by external clock  
Floating, pulled by external clock  
EC  
LP, XT and HS  
Feedback inverter disabled at quiescent  
voltage level  
Feedback inverter disabled at quiescent  
voltage level  
Note:  
See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.  
© 2008 Microchip Technology Inc.  
DS39631E-page 31  
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