PIC18F2420/2520/4420/4520
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTRC clock will reach the new frequency within
8 clock cycles (approximately 8 * 32 μs = 256 μs). The
INTOSC clock will stabilize within 1 ms. Code execu-
tion continues during this shift. There is no indication
that the shift has occurred.
2.6
Internal Oscillator Block
The PIC18F2420/2520/4420/4520 devices include an
internal oscillator block which generates two different
clock signals; either can be used as the micro-
controller’s clock source. This may eliminate the need
for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The OSCTUNE register also implements the INTSRC
and PLLEN bits, which control certain features of the
internal oscillator block. The INTSRC bit allows users
to select which internal oscillator provides the clock
source when the 31 kHz frequency option is selected.
This is covered in greater detail in Section 2.7.1
“Oscillator Control Register”.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives a postscaler which can provide a range of
clock frequencies from 31 kHz to 4 MHz. The INTOSC
output is enabled when a clock frequency from 125 kHz
to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source; it is also enabled automatically when any of the
following are enabled:
The PLLEN bit controls the operation of the frequency
multiplier, PLL, in internal oscillator modes.
2.6.4
PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the inter-
nal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
These features are discussed in greater detail in
Section 23.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 30).
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC<3:0> = 1001or 1000). Additionally, the
PLL will only function when the selected output fre-
quency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
2.6.1
INTIO MODES
Using the internal oscillator as the clock source elimi-
nates the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
The PLLEN control bit is only functional in those inter-
nal oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
2.6.5
INTOSC FREQUENCY DRIFT
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz. However, this frequency
may drift as VDD or temperature changes, which can
affect the controller operation in a variety of ways. It is
possible to adjust the INTOSC frequency by modifying
the value in the OSCTUNE register. This has no effect
on the INTRC clock source frequency.
2.6.2
INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz.
The INTRC oscillator operates independently of the
INTOSC source. Any changes in INTOSC across
voltage and temperature are not necessarily reflected
by changes in INTRC and vice versa.
Tuning the INTOSC source requires knowing when to
make the adjustment, in which direction it should be
made, and in some cases, how large a change is
needed. Three compensation techniques are discussed
in Section 2.6.5.1 “Compensating with the
EUSART”, Section 2.6.5.2 “Compensating with the
Timers” and Section 2.6.5.3 “Compensating with the
CCP Module in Capture Mode”, but other techniques
may be used.
2.6.3
OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory but can be adjusted in the user’s applica-
tion. This is done by writing to the OSCTUNE register
(Register 2-1).
DS39631E-page 26
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
