PIC18F45J10 FAMILY
E
F
Effect on Standard PIC Instructions ................................. 296
Effects of Power-Managed Modes on
Fail-Safe Clock Monitor ........................................... 235, 245
Interrupts in Power-Managed Modes ...................... 246
POR or Wake-up from Sleep ................................... 246
WDT During Oscillator Failure ................................. 245
Fast Register Stack ........................................................... 55
Firmware Instructions ...................................................... 249
Flash Configuration Words .............................................. 235
Flash Program Memory ..................................................... 71
Associated Registers ................................................. 79
Control Registers ....................................................... 72
EECON1 and EECON2 ..................................... 72
TABLAT (Table Latch) ....................................... 74
TBLPTR (Table Pointer) .................................... 74
Erase Sequence ........................................................ 76
Erasing ...................................................................... 76
Operation During Code-Protect ................................. 79
Reading ..................................................................... 75
Table Pointer
Boundaries Based on Operation ....................... 74
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Write Sequence ......................................................... 77
Writing To .................................................................. 77
Protection Against Spurious Writes ................... 79
Unexpected Termination ................................... 79
Write Verify ........................................................ 79
FSCM. See Fail-Safe Clock Monitor.
Various Clock Sources ............................................... 32
Electrical Characteristics .................................................. 303
Enhanced Capture/Compare/PWM (ECCP) .................... 135
Associated Registers ............................................... 148
Capture and Compare Modes .................................. 136
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration ....................................... 136
Pin Configurations for ECCP1 Modes ...................... 136
PWM Mode. See PWM (ECCP Module).
Standard PWM Mode ............................................... 136
Timer Resources ...................................................... 136
Enhanced PWM Mode. See PWM (ECCP Module). ........ 137
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................ 220
A/D Minimum Charging Time ................................... 220
Errata ................................................................................... 6
EUSART
Asynchronous Mode ................................................ 203
12-Bit Break Transmit and Receive ................. 208
Associated Registers, Receive ........................ 206
Associated Registers, Transmit ....................... 204
Auto-Wake-up on Sync Break ......................... 206
Receiver ........................................................... 205
Setting Up 9-Bit Mode with
G
Address Detect ........................................ 205
GOTO .............................................................................. 270
Transmitter ....................................................... 203
Baud Rate Generator
H
Operation in Power-Managed Mode ................ 197
Baud Rate Generator (BRG) .................................... 197
Associated Registers ....................................... 198
Auto-Baud Rate Detect .................................... 201
Baud Rate Error, Calculating ........................... 198
Baud Rates, Asynchronous Modes ................. 199
High Baud Rate Select (BRGH Bit) ................. 197
Sampling .......................................................... 197
Synchronous Master Mode ...................................... 209
Associated Registers, Receive ........................ 211
Associated Registers, Transmit ....................... 210
Reception ......................................................... 211
Transmission ................................................... 209
Synchronous Slave Mode ........................................ 212
Associated Registers, Receive ........................ 213
Associated Registers, Transmit ....................... 212
Reception ......................................................... 213
Transmission ................................................... 212
Extended Instruction Set
ADDFSR .................................................................. 292
ADDULNK ................................................................ 292
and Using MPLAB IDE Tools ................................... 298
CALLW ..................................................................... 293
Considerations for Use ............................................ 296
MOVSF .................................................................... 293
MOVSS .................................................................... 294
PUSHL ..................................................................... 294
SUBFSR .................................................................. 295
SUBULNK ................................................................ 295
Syntax ...................................................................... 291
External Clock Input (EC Modes) ....................................... 28
Hardware Multiplier ............................................................ 81
Introduction ................................................................ 81
Operation ................................................................... 81
Performance Comparison .......................................... 81
I
I/O Ports ............................................................................ 97
2
I C Mode (MSSP)
Acknowledge Sequence Timing .............................. 185
Associated Registers ............................................... 192
Baud Rate Generator .............................................. 178
Bus Collision
During a Repeated Start Condition .................. 190
During a Stop Condition .................................. 191
Clock Arbitration ...................................................... 179
Clock Stretching ...................................................... 171
10-Bit Slave Receive Mode (SEN = 1) ............ 171
10-Bit Slave Transmit Mode ............................ 171
7-Bit Slave Receive Mode (SEN = 1) .............. 171
7-Bit Slave Transmit Mode .............................. 171
Clock Synchronization and the CKP Bit .................. 172
Effects of a Reset .................................................... 186
General Call Address Support ................................. 175
2
I C Clock Rate w/BRG ............................................ 178
Master Mode ............................................................ 176
Baud Rate Generator ...................................... 178
Operation ......................................................... 177
Reception ........................................................ 182
Repeated Start Condition Timing .................... 181
Start Condition Timing ..................................... 180
Transmission ................................................... 182
© 2009 Microchip Technology Inc.
DS39682E-page 355
MICROCHIP [ MICROCHIP ]
