PIC18F45J10 FAMILY
TABLE 10-11: PORTE I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RE0/RD/AN5
RE0
0
1
1
1
0
1
1
1
0
1
1
1
O
I
DIG
ST
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
RD
I
TTL
ANA
DIG
ST
AN5
RE1
I
A/D Input Channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
RE1/WR/AN6
RE2/CS/AN7
O
I
WR
AN6
RE2
I
TTL
ANA
DIG
ST
I
A/D Input Channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
O
I
CS
I
TTL
ANA
AN7
I
A/D Input Channel 7; default input configuration on POR.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE(1)
LATE(1)
—
—
—
—
—
—
—
—
—
—
RE2
RE1
RE0
50
50
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE(1)
ADCON1
IBF
—
OBF
—
IBOV
PSPMODE
VCFG0
—
TRISE2
PCFG2
TRISE1
PCFG1
TRISE0
PCFG0
50
48
VCFG1
PCFG3
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: These registers are not available in 28-pin devices.
DS39682E-page 112
© 2009 Microchip Technology Inc.
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