PIC18F45J10 FAMILY
TABLE 10-9: PORTD I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RD0/PSP0/SCK2/
SCL2
RD0
0
1
x
x
0
1
0
1
O
I
DIG
ST
LATD<0> data output.
PORTD<0> data input.
PSP0
SCK2
SCL2
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<0>); takes priority over port data.
PSP write data input.
O
I
SPI clock output (MSSP2 module); takes priority over port data.
SPI clock input (MSSP2 module).
2
O
I
DIG
I C™ clock output (MSSP2 module); takes priority over port data.
2
2
I C/SMB I C clock input (MSSP2 module); input type depends on module setting.
RD1/PSP1/SDI2/
SDA2
RD1
0
1
x
x
1
1
1
0
1
x
x
0
0
1
x
x
1
0
1
x
x
0
1
x
x
0
O
I
DIG
ST
LATD<1> data output.
PORTD<1> data input.
PSP1
O
I
DIG
TTL
ST
PSP read data output (LATD<1>); takes priority over port data.
PSP write data input.
SDI2
I
SPI data input (MSSP2 module).
2
SDA2
O
I
DIG
I C data output (MSSP2 module); takes priority over port data.
2
2
I C/SMB I C data input (MSSP2 module); input type depends on module setting.
RD2/PSP2/SDO2
RD3/PSP3/SS2
RD2
O
I
DIG
ST
LATD<2> data output.
PORTD<2> data input.
PSP2
O
I
DIG
TTL
DIG
DIG
ST
PSP read data output (LATD<2>); takes priority over port data.
PSP write data input.
SDO2
RD3
O
O
I
SPI data output (MSSP2 module); takes priority over port data.
LATD<3> data output.
PORTD<3> data input.
PSP3
O
I
DIG
TTL
TTL
DIG
ST
PSP read data output (LATD<3>); takes priority over port data.
PSP write data input.
SS2
RD4
I
Slave select input for MSSP2 (MSSP2 module).
LATD<4> data output.
RD4/PSP4
O
I
PORTD<4> data input.
PSP4
RD5
O
I
DIG
TTL
DIG
ST
PSP read data output (LATD<4>); takes priority over port data.
PSP write data input.
RD5/PSP5/P1B
O
I
LATD<5> data output.
PORTD<5> data input.
PSP5
O
I
DIG
TTL
DIG
PSP read data output (LATD<5>); takes priority over port data.
PSP write data input.
P1B
RD6
O
ECCP1 Enhanced PWM output, Channel B; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
RD6/PSP6/P1C
RD7/PSP7/P1D
0
1
x
x
0
O
I
DIG
ST
LATD<6> data output.
PORTD<6> data input.
PSP6
O
I
DIG
TTL
DIG
PSP read data output (LATD<6>); takes priority over port data.
PSP write data input.
P1C
RD7
O
ECCP1 Enhanced PWM output, Channel C; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
0
1
x
x
0
O
I
DIG
ST
LATD<7> data output.
PORTD<7> data input.
PSP7
P1D
O
I
DIG
TTL
DIG
PSP read data output (LATD<7>); takes priority over port data.
PSP write data input.
O
ECCP1 Enhanced PWM output, Channel D; takes priority over port and PSP
data. May be configured for tri-state during Enhanced PWM shutdown events.
2
2
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I C™/SMB = I C/SMBus input buffer;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
DS39682E-page 108
© 2009 Microchip Technology Inc.
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