PIC18F45J10 FAMILY
FIGURE 10-4:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-5:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-13: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Reset
Values
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD(1)
LATD(1)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RE0
50
50
50
50
50
PORTD Data Latch Register (Read and Write to Data Latch)
TRISD(1) PORTD Data Direction Control Register
PORTE(1)
LATE(1)
—
—
—
—
—
—
—
—
—
—
RE2
RE1
PORTE Data Latch Register
(Read and Write to Data Latch)
TRISE(1)
INTCON
PIR1
IBF
OBF
IBOV
PSPMODE
INT0IE
TXIF
—
TRISE2
TMR0IF
CCP1IF
TRISE1
INT0IF
TRISE0
RBIF
50
47
49
49
49
48
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
PSPIF(1)
PSPIE(1)
PSPIP(1)
—
ADIF
ADIE
ADIP
—
RCIF
RCIE
SSP1IF
SSP1IE
SSP1IP
PCFG3
TMR2IF
TMR1IF
PIE1
TXIE
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
IPR1
RCIP
TXIP
ADCON1
VCFG1
VCFG0
PCFG2
PCFG1
PCFG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers and/or bits are not implemented on 28-pin devices and should be read as ‘0’.
DS39682E-page 114
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
