PIC18F45J10 FAMILY
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
10.6 PORTE, TRISE and LATE
Registers
Note:
PORTE is only available in 40/44-pin
devices.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
Depending on the particular PIC18F45J10 family
device selected, PORTE is implemented in two
different ways.
EXAMPLE 10-6:
INITIALIZING PORTE
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as analog inputs, these pins will read as ‘0’s.
CLRF
PORTE
; Initialize PORTE by
; clearing output
; data latches
CLRF
LATE
; Alternate method
; to clear output
; data latches
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
MOVLW 0Ah
; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 03h
; Value used to
; initialize data
; direction
MOVWF TRISE
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note:
On a Power-on Reset, RE<2:0> are
configured as analog inputs.
DS39682E-page 110
© 2009 Microchip Technology Inc.
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