PIC18F45J10 FAMILY
TABLE 10-7: PORTC I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RC0/T1OSO/
T1CKI
RC0
0
1
x
O
I
DIG
ST
LATC<0> data output.
PORTC<0> data input.
T1OSO
O
ANA
Timer1 oscillator output; enabled when Timer1 oscillator enabled.
Disables digital I/O.
T1CKI
RC1
1
0
1
x
I
O
I
ST
DIG
ST
Timer1 counter input.
LATC<1> data output.
PORTC<1> data input.
RC1/T1OSI/CCP2
T1OSI
I
ANA
Timer1 oscillator input; enabled when Timer1 oscillator enabled.
Disables digital I/O.
(1)
CCP2
0
1
0
1
0
1
0
O
I
DIG
ST
CCP2 compare and PWM output; takes priority over port data.
CCP2 capture input.
RC2/CCP1/P1A
RC2
O
I
DIG
ST
LATC<2> data output.
PORTC<2> data input.
CCP1
O
I
DIG
ST
ECCP1/CCP1 compare or PWM output; takes priority over port data.
ECCP1/CCP1 capture input.
(2)
P1A
O
DIG
ECCP1 Enhanced PWM output, channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority over
port data.
RC3/SCK1/SCL1
RC3
SCK1
SCL1
RC4
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
O
I
DIG
ST
LATC<3> data output.
PORTC<3> data input.
O
I
DIG
ST
SPI clock output (MSSP1 module); takes priority over port data.
SPI clock input (MSSP1 module).
2
O
I
DIG
I C™ clock output (MSSP1 module); takes priority over port data.
2
2
I C/SMB I C clock input (MSSP1 module); input type depends on module setting.
RC4/SDI1/SDA1
O
I
DIG
ST
LATC<4> data output.
PORTC<4> data input.
SDI1
I
ST
SPI data input (MSSP1 module).
2
SDA1
O
I
DIG
I C data output (MSSP1 module); takes priority over port data.
2
2
I C/SMB I C data input (MSSP1 module); input type depends on module setting.
RC5/SDO1
RC6/TX/CK
RC5
O
I
DIG
ST
LATC<5> data output.
PORTC<5> data input.
SDO1
RC6
O
O
I
DIG
DIG
ST
SPI data output (MSSP1 module); takes priority over port data.
LATC<6> data output.
PORTC<6> data input.
TX
CK
O
DIG
Asynchronous serial transmit data output (EUSART module);
takes priority over port data. User must configure as output.
1
O
DIG
Synchronous serial clock output (EUSART module); takes priority
over port data.
1
0
1
1
1
I
O
I
ST
DIG
ST
Synchronous serial clock input (EUSART module).
LATC<7> data output.
RC7/RX/DT
RC7
PORTC<7> data input.
RX
DT
I
ST
Asynchronous serial receive data input (EUSART module).
O
DIG
Synchronous serial data output (EUSART module); takes priority over
port data.
1
I
ST
Synchronous serial data input (EUSART module). User must
configure as an input.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
I C™/SMB = I C/SMBus input buffer; x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
2
2
Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set. Alternate assignment is RB3.
2: Enhanced PWM output is available only on PIC18F44J10/45J10 devices.
© 2009 Microchip Technology Inc.
DS39682E-page 105
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