PIC18F45J10 FAMILY
TABLE 10-5: PORTB I/O SUMMARY
TRIS
Setting
I/O
Type
Pin
Function
I/O
Description
RB0/INT0/FLT0/
AN12
RB0
0
1
O
I
DIG
TTL
LATB<0> data output; not affected by analog input.
PORTB<0> data input; weak pull-up when RBPU bit is cleared.
(1)
Disabled when analog input enabled.
INT0
FLT0
1
1
I
I
ST
ST
External Interrupt 0 input.
PWM Fault input (ECCP1/CCP1 module); enabled in
software.
(1)
AN12
RB1
1
0
1
I
O
I
ANA
DIG
TTL
A/D Input Channel 12.
RB1/INT1/AN10
RB2/INT2/AN8
RB3/AN9/CCP2
LATB<1> data output; not affected by analog input.
PORTB<1> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
INT1
AN10
RB2
1
1
0
1
I
I
ST
ANA
DIG
TTL
External Interrupt 1 input.
(1)
A/D Input Channel 10.
O
I
LATB<2> data output; not affected by analog input.
PORTB<2> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
INT2
AN8
RB3
1
1
0
1
I
I
ST
ANA
DIG
TTL
External Interrupt 2 input.
(1)
A/D Input Channel 8.
O
I
LATB<3> data output; not affected by analog input.
PORTB<3> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
(1)
AN9
1
0
1
0
1
I
O
I
ANA
DIG
ST
A/D Input Channel 9.
(2)
CCP2
CCP2 compare and PWM output.
CCP2 capture input
RB4/KBI0/AN11
RB4
O
I
DIG
TTL
LATB<4> data output; not affected by analog input.
PORTB<4> data input; weak pull-up when RBPU bit is cleared.
Disabled when analog input enabled.
(1)
KBI0
AN11
RB5
1
1
0
1
1
1
0
I
I
TTL
ANA
DIG
TTL
TTL
ST
Interrupt-on-change pin.
(1)
A/D Input Channel 11.
RB5/KBI1/T0CKI/
C1OUT
O
I
LATB<5> data output.
PORTB<5> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
KBI1
T0CKI
C1OUT
I
I
Timer0 clock input.
O
DIG
Comparator 1 output; takes priority over port data.
RB6/KBI2/PGC
RB7/KBI3/PGD
RB6
0
1
1
x
0
1
1
x
x
O
I
DIG
TTL
TTL
ST
LATB<6> data output.
PORTB<6> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
KBI2
PGC
RB7
I
(3)
I
Serial execution (ICSP™) clock input for ICSP and ICD operation.
LATB<7> data output.
O
I
DIG
TTL
TTL
DIG
ST
PORTB<7> data input; weak pull-up when RBPU bit is cleared.
Interrupt-on-change pin.
KBI3
PGD
I
(3)
O
I
Serial execution data output for ICSP and ICD operation.
(3)
Serial execution data input for ICSP and ICD operation.
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x= Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Note 1: Pins are configured as analog inputs by default.
2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
3: All other pin functions are disabled when ICSP™ or ICD are enabled.
DS39682E-page 102
© 2009 Microchip Technology Inc.
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