PIC18F2450/4450
FIGURE 5-8:
COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND
BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
000h
When a = 0 and f ≥ 60h:
The instruction executes in
Direct Forced mode. ‘f’ is inter-
preted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
the SFRs or locations F60h to
0FFh (Bank 15) of data
memory.
060h
080h
Bank 0
100h
00h
60h
Bank 1
through
Bank 14
Valid range
for ‘f’
FFh
F00h
F60h
Access RAM
Locations below 60h are not
available in this addressing
mode.
Bank 15
SFRs
FFFh
Data Memory
When a = 0 and f ≤ 5Fh:
000h
080h
100h
Bank 0
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
001001da ffffffff
Bank 1
through
Bank 14
FSR2H
FSR2L
F00h
F60h
Bank 15
Note that in this mode, the
correct syntax is now:
SFRs
ADDWF [k], d
where ‘k’ is the same as ‘f’.
FFFh
Data Memory
BSR
000h
080h
100h
00000000
When a = 1 (all values of f):
Bank 0
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is inter-
preted as a location in one of
the 16 banks of the data
memory space. The bank is
designated by the Bank Select
Register (BSR). The address
can be in any implemented
bank in the data memory
space.
001001da ffffffff
Bank 1
through
Bank 14
F00h
F60h
Bank 15
SFRs
FFFh
Data Memory
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 71
MICROCHIP [ MICROCHIP ]
