欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F2450-I/SO的Datasheet PDF文件第67页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第68页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第69页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第70页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第72页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第73页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第74页浏览型号PIC18F2450-I/SO的Datasheet PDF文件第75页  
PIC18F2450/4450  
5.4.3.2  
FSR Registers and POSTINC,  
5.4.3.3  
Operations by FSRs on FSRs  
POSTDEC, PREINC and PLUSW  
Indirect Addressing operations that target other FSRs  
or virtual registers represent special cases. For  
example, using an FSR to point to one of the virtual  
registers will not result in successful operations. As a  
specific case, assume that FSR0H:FSR0L contains  
FE7h, the address of INDF1. Attempts to read the  
value of INDF1, using INDF0 as an operand, will return  
00h. Attempts to write to INDF1, using INDF0 as the  
operand, will result in a NOP.  
In addition to the INDF operand, each FSR register pair  
also has four additional indirect operands. Like INDF,  
these are “virtual” registers that cannot be indirectly  
read or written to. Accessing these registers actually  
accesses the associated FSR register pair, but also  
performs a specific action on it stored value. They are:  
• POSTDEC: accesses the FSR value, then  
automatically decrements it by ‘1’ afterwards  
On the other hand, using the virtual registers to write to  
an FSR pair may not occur as planned. In these cases,  
the value will be written to the FSR pair but without any  
incrementing or decrementing. Thus, writing to INDF2  
or POSTDEC2 will write the same value to the  
FSR2H:FSR2L.  
• POSTINC: accesses the FSR value, then  
automatically increments it by ‘1’ afterwards  
• PREINC: increments the FSR value by ‘1’, then  
uses it in the operation  
• PLUSW: adds the signed value of the W register  
(range of -127 to 128) to that of the FSR and uses  
the new value in the operation.  
Since the FSRs are physical registers mapped in the  
SFR space, they can be manipulated through all direct  
operations. Users should proceed cautiously when  
working on these registers, particularly if their code  
uses Indirect Addressing.  
In this context, accessing an INDF register uses the  
value in the FSR registers without changing them.  
Similarly, accessing a PLUSW register gives the FSR  
value offset by that in the W register; neither value is  
actually changed in the operation. Accessing the other  
virtual registers changes the value of the FSR  
registers.  
Similarly, operations by Indirect Addressing are  
generally permitted on all other SFRs. Users should  
exercise the appropriate caution that they do not  
inadvertently change settings that might affect the  
operation of the device.  
Operations on the FSRs with POSTDEC, POSTINC  
and PREINC affect the entire register pair; that is,  
rollovers of the FSRnL register from FFh to 00h carry  
over to the FSRnH register. On the other hand, results  
of these operations do not change the value of any  
flags in the STATUS register (e.g., Z, N, OV, etc.).  
The PLUSW register can be used to implement a form  
of Indexed Addressing in the data memory space. By  
manipulating the value in the W register, users can  
reach addresses that are fixed offsets from pointer  
addresses. In some applications, this can be used to  
implement some powerful program control structure,  
such as software stacks, inside of data memory.  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 69  
 复制成功!