PIC18F2450/4450
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
4.0
RESET
The PIC18F2450/4450 devices differentiate between
various kinds of Reset:
4.1
RCON Register
a) Power-on Reset (POR)
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be cleared
by the event and must be set by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
Section 4.6 “Reset State of Registers”.
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESETInstruction
g) Stack Full Reset
h) Stack Underflow Reset
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 8.0 “Interrupts”. BOR is covered in
Section 4.4 “Brown-out Reset (BOR)”.
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 18.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESETInstruction
Stack Full/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
( )_IDLE
Sleep
WDT
Time-out
VDD Rise
Detect
POR Pulse
BOREN
VDD
Brown-out
Reset
S
OST/PWRT
OST
10-bit Ripple Counter
1024 Cycles
Chip_Reset
R
Q
OSC1
32 μs
65.5 ms
PWRT
11-bit Ripple Counter
INTRC(1)
Enable PWRT
(2)
Enable OST
Note 1: This is the INTRC source from the internal oscillator and is separate from the RC oscillator of the CLKI pin.
2: See Table 4-2 for time-out situations.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 41
MICROCHIP [ MICROCHIP ]
