PIC18F2450/4450
In these instances, the primary clock source either
does not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (EC and any internal
oscillator modes). However, a fixed delay of interval
TCSD following the wake event is still required when
leaving Sleep and Idle modes to allow the CPU to
prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
3.5.4
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
is not stopped; and
• the primary clock source is not any of the XT or
HS modes.
TABLE 3-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Microcontroller Clock Source
Clock Ready Status
Exit Delay
Bit (OSCCON)
Before Wake-up
After Wake-up
XT, HS
XTPLL, HSPLL
EC
Primary Device Clock
(PRI_IDLE mode)
None
OSTS
OSTS
OSTS
OSTS
INTRC(1)
(3)
XT, HS
TOST
(3)
(3)
(3)
XTPLL, HSPLL
EC
TOST + trc
T1OSC or INTRC(1)
(2)
TCSD
INTRC(1)
TIOBST
(4)
(3)
XT, HS
TOST
XTPLL, HSPLL
EC
TOST + trc
INTRC(1)
(2)
TCSD
INTRC(1)
None
(3)
XT, HS
TOST
XTPLL, HSPLL
EC
TOST + trc
None
(Sleep mode)
(2)
TCSD
(4)
INTRC(1)
TIOBST
Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.
2: TCSD (parameter 38, Table 21-10) is a required delay when waking from Sleep and all Idle modes and runs
concurrently with any other required delays (see Section 3.4 “Idle Modes”).
3: TOST is the Oscillator Start-up Timer period (parameter 32, Table 21-10). trc is the PLL lock time-out
(parameter F12, Table 21-7); it is also designated as TPLL.
4: Execution continues during TIOBST (parameter 39, Table 21-10), the INTRC stabilization period.
DS39760A-page 40
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© 2006 Microchip Technology Inc.
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