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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
FIGURE 4-2:  
EXTERNAL POWER-ON  
RESET CIRCUIT (FOR  
SLOW VDD POWER-UP)  
4.2  
Master Clear Reset (MCLR)  
The MCLR pin provides a method for triggering an  
external Reset of the device. A Reset is generated by  
holding the pin low. These devices have a noise filter in  
the MCLR Reset path which detects and ignores small  
pulses.  
VDD  
VDD  
The MCLR pin is not driven low by any internal Resets,  
including the WDT.  
D
R
R1  
MCLR  
In PIC18F2450/4450 devices, the MCLR input can be  
disabled with the MCLRE Configuration bit. When  
MCLR is disabled, the pin becomes a digital input. See  
Section 9.5 “PORTE, TRISE and LATE Registers”  
for more information.  
PIC18FXXXX  
C
Note 1: External Power-on Reset circuit is required  
only if the VDD power-up slope is too slow.  
The diode D helps discharge the capacitor  
quickly when VDD powers down.  
4.3  
Power-on Reset (POR)  
A
Power-on Reset pulse is generated on-chip  
2: R < 40 kΩ is recommended to make sure that  
the voltage drop across R does not violate  
the device’s electrical specification.  
whenever VDD rises above a certain threshold. This  
allows the device to start in the initialized state when  
VDD is adequate for operation.  
3: R1 1 kΩ will limit any current flowing into  
MCLR from external capacitor C, in the event  
of MCLR/VPP pin breakdown, due to Electro-  
static Discharge (ESD) or Electrical  
Overstress (EOS).  
To take advantage of the POR circuitry, tie the MCLR pin  
through a resistor (1 kΩ to 10 kΩ) to VDD. This will  
eliminate external RC components usually needed to  
create a Power-on Reset delay. A minimum rise rate for  
VDD is specified (parameter D004, Section267 “DC  
Characteristics”). For a slow rise time, see Figure 4-2.  
When the device starts normal operation (i.e., exits the  
Reset condition), device operating parameters (volt-  
age, frequency, temperature, etc.) must be met to  
ensure operation. If these conditions are not met, the  
device must be held in Reset until the operating  
conditions are met.  
POR events are captured by the POR bit (RCON<1>).  
The state of the bit is set to ‘0’ whenever a POR occurs;  
it does not change for any other Reset event. POR is  
not reset to ‘1’ by any hardware event. To capture  
multiple events, the user manually resets the bit to ‘1’  
in software following any POR.  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 43