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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
3.1.3  
CLOCK TRANSITIONS AND  
STATUS INDICATORS  
3.2.1  
PRI_RUN MODE  
The PRI_RUN mode is the normal, full power execution  
mode of the microcontroller. This is also the default  
mode upon a device Reset unless Two-Speed Start-up  
is enabled (see Section 18.3 “Two-Speed Start-up”  
for details). In this mode, the OSTS bit is set.  
The length of the transition between clock sources is  
the sum of two cycles of the old clock source and three  
to four cycles of the new clock source. This formula  
assumes that the new clock source is stable.  
Two bits indicate the current clock source and its  
status. They are:  
3.2.2  
SEC_RUN MODE  
The SEC_RUN mode is the compatible mode to the  
“clock switching” feature offered in other PIC18  
devices. In this mode, the CPU and peripherals are  
clocked from the Timer1 oscillator. This gives users the  
option of lower power consumption while still using a  
high accuracy clock source.  
• OSTS (OSCCON<3>)  
• T1RUN (T1CON<6>)  
In general, only one of these bits will be set while in a  
given power-managed mode. When the OSTS bit is  
set, the primary clock is providing the device clock.  
When the T1RUN bit is set, the Timer1 oscillator is  
providing the clock.  
SEC_RUN mode is entered by setting the SCS1:SCS0  
bits to ‘01’. The device clock source is switched to the  
Timer1 oscillator (see Figure 3-1), the primary  
oscillator is shut down, the T1RUN bit (T1CON<6>) is  
set and the OSTS bit is cleared.  
Note:  
Executing a SLEEP instruction does not  
necessarily place the device into Sleep  
mode. It acts as the trigger to place the  
controller into either the Sleep mode, or  
one of the Idle modes, depending on the  
setting of the IDLEN bit.  
Note:  
The Timer1 oscillator should already be  
running prior to entering SEC_RUN mode.  
If the T1OSCEN bit is not set when the  
SCS1:SCS0 bits are set to ‘01’, entry to  
SEC_RUN mode will not occur. If the  
Timer1 oscillator is enabled but not yet  
running, device clocks will be delayed until  
the oscillator has started. In such  
situations, initial oscillator operation is far  
from stable and unpredictable operation  
may result.  
3.1.4  
MULTIPLE SLEEP COMMANDS  
The power-managed mode that is invoked with the  
SLEEP instruction is determined by the setting of the  
IDLEN bit at the time the instruction is executed. If  
another SLEEPinstruction is executed, the device will  
enter the power-managed mode specified by IDLEN at  
that time. If IDLEN has changed, the device will enter  
the new power-managed mode specified by the new  
setting.  
On transitions from SEC_RUN mode to PRI_RUN, the  
peripherals and CPU continue to be clocked from the  
Timer1 oscillator while the primary clock is started.  
When the primary clock becomes ready, a clock switch  
back to the primary clock occurs (see Figure 3-2).  
When the clock switch is complete, the T1RUN bit is  
cleared, the OSTS bit is set and the primary clock is  
providing the clock. The IDLEN and SCS bits are not  
affected by the wake-up; the Timer1 oscillator  
continues to run.  
3.2  
Run Modes  
In the Run modes, clocks to both the core and  
peripherals are active. The difference between these  
modes is the clock source.  
FIGURE 3-1:  
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE  
Q1 Q2 Q3 Q4 Q1  
Q2  
Q3  
Q4  
Q1  
Q2  
Q3  
1
2
3
n-1  
n
T1OSI  
OSC1  
Clock Transition(1)  
CPU  
Clock  
Peripheral  
Clock  
Program  
Counter  
PC  
PC + 2  
PC + 4  
Note 1: Clock transition typically occurs within 2-4 TOSC.  
DS39760A-page 34  
Advance Information  
© 2006 Microchip Technology Inc.  
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