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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
FIGURE 3-2:  
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)  
Q1  
Q2  
Q3  
Q4  
Q1  
Q2 Q3 Q4 Q1 Q2 Q3  
T1OSI  
OSC1  
(1)  
TOST  
(1)  
TPLL  
1
2
n-1  
n
PLL Clock  
Output  
Clock(2)  
Transition  
CPU Clock  
Peripheral  
Clock  
Program  
Counter  
PC + 2  
PC + 4  
PC  
SCS1:SCS0 bits Changed  
OSTS bit Set  
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.  
2: Clock transition typically occurs within 2-4 TOSC.  
This mode is entered by setting SCS1 to ‘1’. Although  
it is ignored, it is recommended that SCS0 also be  
cleared; this is to maintain software compatibility with  
future devices. When the clock source is switched to  
the INTRC (see Figure 3-3), the primary oscillator is  
shut down and the OSTS bit is cleared.  
3.2.3  
RC_RUN MODE  
In RC_RUN mode, the CPU and peripherals are  
clocked from the internal oscillator; the primary clock is  
shut down. When using the INTRC source, this mode  
provides the best power conservation of all the Run  
modes while still executing code. It works well for user  
applications which are not highly timing sensitive or do  
not require high-speed clocks at all times.  
On transitions from RC_RUN mode to PRI_RUN mode,  
the device continues to be clocked from the INTRC  
while the primary clock is started. When the primary  
clock becomes ready, a clock switch to the primary  
clock occurs (see Figure 3-4). When the clock switch is  
complete, the OSTS bit is set and the primary clock is  
providing the device clock. The IDLEN and SCS bits  
are not affected by the switch. The INTRC source will  
continue to run if either the WDT or the Fail-Safe Clock  
Monitor is enabled.  
If the primary clock source is the internal oscillator  
(INTRC), there are no distinguishable differences  
between the PRI_RUN and RC_RUN modes during  
execution. However, a clock switch delay will occur dur-  
ing entry to and exit from RC_RUN mode. Therefore, if  
the primary clock source is the internal oscillator, the  
use of RC_RUN mode is not recommended.  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 35  
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