PIC18F2450/4450
In all other power-managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
18.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code
execution, by allowing the microcontroller to use the
INTRC oscillator as a clock source until the primary
clock source is available. It is enabled by setting the
IESO Configuration bit.
18.3.1
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
Two-Speed Start-up should be enabled only if the
primary oscillator mode is XT, HS, XTPLL or HSPLL
(Crystal-based modes). Other sources do not require
an OST start-up delay; for these, Two-Speed Start-up
should be disabled.
While using the INTRC oscillator in Two-Speed Start-up,
the device still obeys the normal command sequences
for entering power-managed modes, including serial
SLEEP instructions (refer to Section 3.1.4 “Multiple
Sleep Commands”). In practice, this means that user
code can change the SCS1:SCS0 bit settings or issue
SLEEPinstructions before the OST times out. This would
allow an application to briefly wake-up, perform routine
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator is providing the clock during
wake-up from Reset or Sleep mode.
Because the OSCCON register is cleared on Reset
events, the INTRC clock is used directly at its base
frequency.
FIGURE 18-2:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
Q1
Q2
INTRC
OSC1
(1)
(1)
TPLL
TOST
1
2
n-1
n
PLL Clock
Output
Clock
Transition
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
OSTS bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 4
PC + 6
Wake from Interrupt Event
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 203
MICROCHIP [ MICROCHIP ]
