PIC18F2450/4450
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures207 through208 illustrate
table write and table read protection.
18.5.1
PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
Chip Erase or Block Erase function. The
full Chip Erase and Block Erase functions
can only be initiated via ICSP operation or
an external programmer.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
FIGURE 18-6:
TABLE WRITE (WRTn) DISALLOWED
Register Values
Program Memory
Configuration Bit Settings
000000h
0007FFh
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
000FFFh
001000h
TBLPTR = 0008FFh
PC = 001FFEh
TBLWT*
001FFFh
002000h
003FFFh
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
Results: All table writes disabled to Blockn whenever WRTn = 0.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 207
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