PIC18F2450/4450
Each of the three blocks has three code protection bits
associated with them. They are:
18.5 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro® devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 18-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 18-3.
The user program memory is divided into three blocks.
One of these is a boot block of 1 or 2 Kbytes. The
remainder of the memory is divided into two blocks on
binary boundaries.
FIGURE 18-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2450/4450
MEMORY SIZE/DEVICE
Block Code Protection
Controlled By:
16 Kbytes
(PIC18F2450/4450)
Address
Range
000000h
0007FFh
000FFFh
Boot Block
Block 0
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
001000h
001FFFh
002000h
Block 1
003FFFh
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 18-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
300008h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
—
—
—
—
—
—
—
CPB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CP1
—
CP0
—
300009h
30000Ah
30000Bh
30000Ch
30000Dh
—
WRT1
—
WRT0
—
WRTB
—
WRTC
—
EBTR1
—
EBTR0
—
EBTRB
—
Legend: Shaded cells are unimplemented.
DS39760A-page 206
Advance Information
© 2006 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
