PIC18F2450/4450
18.2 Watchdog Timer (WDT)
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
For PIC18F2450/4450 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
2: When a CLRWDTinstruction is executed,
the postscaler count will be cleared.
18.2.1
CONTROL REGISTER
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
Register 18-15 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
selected by
a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 131.072 seconds (2.18 minutes). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEPor CLRWDTinstruction
is executed or a clock failure has occurred.
.
FIGURE 18-1:
WDT BLOCK DIAGRAM
Enable WDT
SWDTEN
WDTEN
INTRC Control
WDT Counter
Wake-up from
Power-Managed
Modes
÷128
INTRC Source
WDT
Reset
Reset
CLRWDT
All Device Resets
Programmable Postscaler
1:1 to 1:32,768
WDT
4
WDTPS<3:0>
SLEEP
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 201
MICROCHIP [ MICROCHIP ]
