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PIC18F2450-I/SO 参数 Datasheet PDF下载

PIC18F2450-I/SO图片预览
型号: PIC18F2450-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,高性能, 12 MIPS ,增强型闪存, USB微控制器采用纳瓦技术 [28/40/44-Pin, High-Performance, 12 MIPS, Enhanced Flash, USB Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 320 页 / 5591 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2450/4450  
The value in the ADRESH:ADRESL registers is not  
modified for a Power-on Reset. The ADRESH:ADRESL  
registers will contain unknown data after a Power-on  
Reset.  
5. Wait for A/D conversion to complete, by either:  
• Polling for the GO/DONE bit to be cleared  
OR  
• Waiting for the A/D interrupt  
After the A/D module has been configured as desired, the  
selected channel must be acquired before the conver-  
sion is started. The analog input channels must have  
their corresponding TRIS bits selected as an input. To  
determine acquisition time, see Section 16.1 “A/D  
Acquisition Requirements”. After this acquisition time  
has elapsed, the A/D conversion can be started. An  
acquisition time can be programmed to occur between  
setting the GO/DONE bit and the actual start of the  
conversion.  
6. Read A/D Result registers (ADRESH:ADRESL);  
clear bit ADIF, if required.  
7. For next conversion, go to step 1 or step 2, as  
required. The A/D conversion time per bit is  
defined as TAD. A minimum wait of 3 TAD is  
required before the next acquisition starts.  
FIGURE 16-2:  
A/D TRANSFER FUNCTION  
The following steps should be followed to perform an  
A/D conversion:  
3FFh  
3FEh  
1. Configure the A/D module:  
• Configure analog pins, voltage reference and  
digital I/O (ADCON1)  
• Select A/D input channel (ADCON0)  
• Select A/D acquisition time (ADCON2)  
• Select A/D conversion clock (ADCON2)  
• Turn on A/D module (ADCON0)  
2. Configure A/D interrupt (if desired):  
• Clear ADIF bit  
003h  
002h  
001h  
000h  
• Set ADIE bit  
• Set GIE bit  
3. Wait the required acquisition time (if required).  
4. Start conversion:  
Analog Input Voltage  
• Set GO/DONE bit (ADCON0 register)  
FIGURE 16-3:  
ANALOG INPUT MODEL  
VDD  
Sampling  
Switch  
VT = 0.6V  
ANx  
SS  
RIC 1k  
RSS  
Rs  
CPIN  
VAIN  
ILEAKAGE  
100 nA  
CHOLD = 25 pF  
VT = 0.6V  
5 pF  
VSS  
Legend: CPIN  
= Input Capacitance  
= Threshold Voltage  
VT  
6V  
5V  
4V  
3V  
2V  
ILEAKAGE = Leakage Current at the pin due to  
various junctions  
VDD  
RIC  
= Interconnect Resistance  
= Sampling Switch  
SS  
CHOLD  
RSS  
= Sample/hold Capacitance (from DAC)  
= Sampling Switch Resistance  
1
2
3
4
(kΩ)  
Sampling Switch  
© 2006 Microchip Technology Inc.  
Advance Information  
DS39760A-page 177