PIC18F2450/4450
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF- pins.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 16-1.
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1100
AN12
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7(1)
0110
AN6(1)
0101
AN5(1)
0100
AN4
VAIN
0011
(Input Voltage)
10-Bit
Converter
A/D
AN3
0010
AN2
0001
VCFG1:VCFG0
AN1
(2)
VDD
0000
AN0
X0
X1
1X
VREF+
VREF-
Reference
Voltage
0X
(2)
VSS
Note 1: Channels AN5 through AN7 are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
DS39760A-page 176
Advance Information
© 2006 Microchip Technology Inc.
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