PIC18F2450/4450
FIGURE 1-2:
PIC18F4450 (40/44-PIN) BLOCK DIAGRAM
Data Bus<8>
PORTA
Table Pointer<21>
RA0/AN0
RA1/AN1
Data Latch
8
8
inc/dec logic
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI/RCV
RA5/AN4/HLVDIN
Data Memory
(2 Kbytes)
PCLATU PCLATH
21
Address Latch
20
OSC2/CLKO/RA6
PCU PCH PCL
Program Counter
12
Data Address<12>
PORTB
PORTC
PORTD
31 Level Stack
STKPTR
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2/VMO
RB3/AN9/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
BSR
12
4
Address Latch
Access
Bank
FSR0
FSR1
FSR2
Program Memory
(24/32 Kbytes)
12
Data Latch
inc/dec
logic
8
Table Latch
Address
Decode
ROM Latch
IR
Instruction Bus <16>
RC0/T1OSO/T1CKI
RC1/T1OSI/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
8 x 8 Multiply
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
3
VDD, VSS
8
Internal
Power-up
Timer
Oscillator
Block
OSC1(2)
OSC2(2)
T1OSI
BITOP
8
W
8
8
Oscillator
Start-up Timer
INTRC
Oscillator
8
8
Power-on
Reset
T1OSO
ALU<8>
8
Watchdog
Timer
ICPGC(3)
ICPGD(3)
ICPORTS(3)
ICRST(3)
MCLR(1)
Single-Supply
Programming
Brown-out
Reset
PORTE
In-Circuit
Debugger
RE0/AN5
RE1/AN6
Fail-Safe
Clock Monitor
Band Gap
Reference
RE2/AN7
MCLR/VPP/RE3(1)
USB Voltage
Regulator
VUSB
BOR
HLVD
Timer0
Timer1
Timer2
ADC
10-bit
EUSART
CCP1
USB
Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer
to Section 2.0 “Oscillator Configurations” for additional information.
3: These pins are only available on 44-pin TQFP under certain conditions. Refer to Section 18.9 “Special ICPORT Features (Designated
Packages Only)” for additional information.
© 2006 Microchip Technology Inc.
Advance Information
DS39760A-page 11
MICROCHIP [ MICROCHIP ]
