PIC18F2420/2520/4420/4520
FIGURE 26-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pins
Note:
Refer to Figure 26-5 for load conditions.
FIGURE 26-9:
BROWN-OUT RESET TIMING
BVDD
VDD
35
VIRVST
Enable Internal
Reference Voltage
Internal Reference
Voltage Stable
36
TABLE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
TmcL
TWDT
MCLR Pulse Width (low)
2
—
—
μs
ms
31
Watchdog Timer Time-out Period
(no postscaler)
3.4
4.1
4.71
32
33
34
TOST
Oscillation Start-up Timer Period
1024 TOSC
55.6
—
65.5
2
1024 TOSC
75.4
—
ms
μs
TOSC = OSC1 period
TPWRT Power-up Timer Period
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—
—
35
36
TBOR
Brown-out Reset Pulse Width
200
—
—
—
μs VDD ≤ BVDD (see D005)
μs
TIRVST Time for Internal Reference
Voltage to become Stable
20
50
37
38
39
TLVD
TCSD
High/Low-Voltage Detect Pulse Width
CPU Start-up Time
200
—
—
10
1
—
—
—
μs
μs
μs
VDD ≤ VLVD
TIOBST Time for INTOSC to Stabilize
—
© 2008 Microchip Technology Inc.
DS39631E-page 345
MICROCHIP [ MICROCHIP ]
