PIC18F2420/2520/4420/4520
FIGURE 26-7:
CLKO AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKO
13
12
19
18
14
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
Note:
Refer to Figure 26-5 for load conditions.
TABLE 26-9: CLKO AND I/O TIMING REQUIREMENTS
Param
Symbol
Characteristic
Min
Typ
Max
Units Conditions
No.
10
TosH2ckL OSC1 ↑ to CLKO ↓
TosH2ckH OSC1 ↑ to CLKO ↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
200
200
100
100
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
11
12
13
14
15
16
17
18
18A
TckR
TckF
CLKO Rise Time
CLKO Fall Time
TckL2ioV CLKO ↓ to Port Out Valid
TioV2ckH Port In Valid before CLKO ↑
TckH2ioI Port In Hold after CLKO ↑
TosH2ioV OSC1 ↑ (Q1 cycle) to Port Out Valid
0.5 TCY + 20 ns
0.25 TCY + 25
—
—
ns
ns
ns
ns
0
—
150
—
TosH2ioI OSC1 ↑ (Q2 cycle) to
Port Input Invalid
PIC18FXXXX
100
200
PIC18LFXXXX
—
ns VDD = 2.0V
(I/O in hold time)
19
TioV2osH Port Input Valid to OSC1 ↑ (I/O in setup
0
—
—
ns
time)
20
TioR
TioF
Port Output Rise Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
—
10
—
10
—
—
—
25
60
25
60
—
—
ns
20A
21
ns VDD = 2.0V
Port Output Fall Time
—
ns
21A
22†
23†
—
ns VDD = 2.0V
TINP
INTx pin High or Low Time
TCY
TCY
ns
ns
TRBP
RB<7:4> Change INTx High or Low Time
†
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
DS39631E-page 344
© 2008 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
