PIC18F45J10 FAMILY
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
7.4
Erasing Flash Program Memory
The minimum erase block is 1024 bytes. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be Bulk
Erased. Word Erase in the Flash array is not supported.
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer register with address of the
block being erased.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 7 bits of the
TBLPTR<21:10> point to the block being erased.
TBLPTR<9:0> are ignored.
2. Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3. Disable interrupts.
4. Write 55h to EECON2.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation.
5. Write 0AAh to EECON2.
6. Set the WR bit. This will begin the erase cycle.
7. The CPU will stall for duration of the erase for
TIE (see parameter D133B).
For protection, the write initiate sequence for EECON2
must be used.
8. Re-enable interrupts.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
EXAMPLE 7-2:
ERASING A FLASH PROGRAM MEMORY BLOCK
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
; load TBLPTR with the base
; address of the memory block
ERASE_ROW
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON1, WREN
EECON1, FREE
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
; enable write to memory
; enable Erase operation
; disable interrupts
Required
Sequence
; write 55h
; write 0AAh
; start erase (CPU stall)
; re-enable interrupts
BSF
DS39682E-page 76
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
