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PIC18F25J10-I/SS 参数 Datasheet PDF下载

PIC18F25J10-I/SS图片预览
型号: PIC18F25J10-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能, RISC微控制器 [28/40/44-Pin High-Performance, RISC Microcontrollers]
分类和应用: 微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 368 页 / 5652 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F45J10 FAMILY  
FIGURE 7-2:  
TABLE WRITE OPERATION  
Instruction: TBLWT*  
Program Memory  
Holding Registers  
(1)  
Table Pointer  
Table Latch (8-bit)  
TABLAT  
TBLPTRU TBLPTRH TBLPTRL  
Program Memory  
(TBLPTR)  
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by  
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in  
Section 7.5 “Writing to Flash Program Memory”.  
The WREN bit, when set, will allow a write operation.  
On power-up, the WREN bit is clear. The WRERR bit is  
set in hardware when the WR bit is set and cleared  
when the internal programming timer expires and the  
write operation is complete.  
7.2  
Control Registers  
Several control registers are used in conjunction with  
the TBLRDand TBLWTinstructions. These include the:  
• EECON1 register  
• EECON2 register  
• TABLAT register  
• TBLPTR registers  
Note:  
During normal operation, the WRERR is  
read as ‘1’. This can indicate that a write  
operation was prematurely terminated by  
a
Reset, or  
a write operation was  
7.2.1  
EECON1 AND EECON2 REGISTERS  
attempted improperly.  
The EECON1 register (Register 7-1) is the control  
register for memory accesses. The EECON2 register is  
not a physical register; it is used exclusively in the  
memory write and erase sequences. Reading  
EECON2 will read all ‘0’s.  
The WR control bit initiates write operations. The bit  
cannot be cleared, only set, in software; it is cleared in  
hardware at the completion of the write operation.  
The FREE bit, when set, will allow a program memory  
erase operation. When FREE is set, the erase  
operation is initiated on the next WR command. When  
FREE is clear, only writes are enabled.  
DS39682E-page 72  
© 2009 Microchip Technology Inc.