PIC18F45J10 FAMILY
7.5.2
WRITE VERIFY
7.5.4
PROTECTION AGAINST
SPURIOUS WRITES
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
To protect against spurious writes to Flash program
memory, the write initiate sequence must also be
followed. See Section 21.0 “Special Features of the
CPU” for more detail.
7.5.3
UNEXPECTED TERMINATION OF
WRITE OPERATION
7.6
Flash Program Operation During
Code Protection
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and repro-
grammed if needed. If the write operation is interrupted
by a MCLR Reset or a WDT Time-out Reset during
normal operation, the user can check the WRERR bit
and rewrite the location(s) as needed.
See Section 21.6 “Program Verification and Code
Protection” for details on code protection of Flash
program memory.
TABLE 7-2:
Name
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Reset
Valueson
page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
47
47
47
47
47
49
49
49
49
49
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
TABLAT
INTCON
Program Memory Table Latch
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
EECON2 EEPROM Control Register 2 (not a physical register)
EECON1
IPR2
—
—
—
—
—
—
FREE
—
WRERR
BCL1IP
BCL1IF
BCL1IE
WREN
—
WR
—
—
OSCFIP
OSCFIF
OSCFIE
CMIP
CMIF
CMIE
CCP2IP
CCP2IF
CCP2IE
PIR2
—
—
—
PIE2
—
—
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.
© 2009 Microchip Technology Inc.
DS39682E-page 79
MICROCHIP [ MICROCHIP ]
