PIC18F45J10 FAMILY
different Reset situations, as indicated in Table 5-1.
These bits are used in software to determine the nature
of the Reset.
5.7
Reset State of Registers
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Table 5-2 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register (CM, RI,
TO, PD, POR and BOR) are set or cleared differently in
TABLE 5-1:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON Register
STKPTR Register
Program
Condition
Counter(1)
CM
RI
TO
PD
POR BOR(2) STKFUL STKUNF
Power-on Reset
0000h
0000h
0000h
0000h
0000h
1
u
1
0
u
1
0
1
u
u
1
u
1
u
1
1
u
1
u
u
0
u
u
u
u
0
u
0
u
u
0
u
u
u
u
0
u
u
u
u
RESETinstruction
Brown-out Reset
Configuration Mismatch Reset
MCLR Reset during
power-managed Run modes
MCLR Reset during
power-managed Idle modes
and Sleep mode
0000h
0000h
u
u
u
u
1
u
0
u
u
u
u
u
u
u
u
u
MCLR Reset during full-power
execution
Stack Full Reset (STVREN = 1)
0000h
0000h
u
u
u
u
u
u
u
u
u
u
u
u
1
u
u
1
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
0000h
PC + 2
u
u
u
u
u
u
u
0
0
u
u
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT time-out during full-power
or power-managed Run modes
WDT time-out during
power-managed Idle or Sleep
modes
Interrupt exit from
PC + 2
u
u
u
0
u
u
u
u
power-managed modes
Legend: u= unchanged
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
2: BOR is not available on PIC18LF2XJ10/4XJ10 devices.
DS39682E-page 46
© 2009 Microchip Technology Inc.
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