PIC18F45J10 FAMILY
TABLE 5-2:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets,
CM Resets
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
INDF2
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
PIC18F2XJ10 PIC18F4XJ10
N/A
N/A
N/A
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
0--- q-00
---- ---0
0-11 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
--00 0qqq
0-00 0000
---- uuuu
uuuu uuuu
---u uuuu
0000 0000
uuuu uuuu
1111 1111
0--- q-00
---- ---0
0-qq qquu
uuuu uuuu
uuuu uuuu
u0uu uuuu
0000 0000
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0-00 0000
--00 0qqq
0-00 0000
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u--- q-uu
---- ---u
u-uu qquu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
--uu uqqq
u-uu uuuu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
WDTCON
RCON(4)
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
DS39682E-page 48
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
