PIC18F45J10 FAMILY
FIGURE 24-13:
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
SSx
70
SCKx
83
(CKP = 0)
71
72
SCKx
(CKP = 1)
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
77
MSb In
74
bit 6 - - - - 1
LSb In
Note: Refer to Figure 24-3 for load conditions.
TABLE 24-17: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TCY
—
ns
TSSL2SCL
71
TSCH
TSCL
TB2B
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25 TCY + 30
—
—
—
—
—
—
ns
71A
72
40
1.25 TCY + 30
40
ns (Note 1)
ns
SCKx Input Low Time
(Slave mode)
72A
73A
74
ns (Note 1)
ns (Note 2)
ns
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
20
75
76
77
80
TDOR
TDOF
SDOx Data Output Rise Time
SDOx Data Output Fall Time
—
—
10
—
25
25
50
50
ns
ns
ns
ns
TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
82
83
TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge
—
50
—
ns
ns
TSCH2SSH, SSx ↑ after SCKx Edge
1.5 TCY + 40
TSCL2SSH
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
DS39682E-page 328
© 2009 Microchip Technology Inc.
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