PIC18F45J10 FAMILY
FIGURE 24-9:
CAPTURE/COMPARE/PWM TIMINGS (INCLUDING ECCP MODULE)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Refer to Figure 24-3 for load conditions.
Note:
TABLE 24-12: CAPTURE/COMPARE/PWM REQUIREMENTS (INCLUDING ECCP MODULE)
Param
Symbol
Characteristic
Min
Max
Units
Conditions
No.
50
TCCL
CCPx Input Low No prescaler
0.5 TCY + 20
—
—
—
—
—
ns
ns
ns
ns
ns
Time
With prescaler
10
0.5 TCY + 20
10
51
52
TCCH
TCCP
CCPx Input
High Time
No prescaler
With prescaler
CCPx Input Period
3 TCY + 40
N
N = prescale
value (1, 4 or 16)
53
54
TCCR
TCCF
CCPx Output Fall Time
CCPx Output Fall Time
—
—
25
25
ns
ns
TABLE 24-13: PARALLEL SLAVE PORT REQUIREMENTS
Param.
Symbol
Characteristic
Min
Max Units
Conditions
No.
62
TdtV2wrH
TwrH2dtI
TrdL2dtV
TrdH2dtI
TibfINH
Data In Valid before WR ↑ or CS ↑ (setup time)
WR ↑ or CS ↑ to Data–In Invalid (hold time)
RD ↓ and CS ↓ to Data–Out Valid
20
20
—
10
—
—
—
ns
ns
ns
ns
63
64
65
66
80
RD ↑ or CS ↓ to Data–Out Invalid
30
Inhibit of the IBF Flag bit being Cleared from
3 TCY
WR ↑ or CS ↑
DS39682E-page 324
© 2009 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
