PIC18F45J10 FAMILY
FIGURE 24-10:
EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)
SSx
70
SCKx
(CKP = 0)
71
72
78
79
79
SCKx
(CKP = 1)
78
80
MSb
bit 6 - - - - - - 1
LSb
SDOx
SDIx
75, 76
MSb In
74
bit 6 - - - - 1
LSb In
73
Note: Refer to Figure 24-3 for load conditions.
TABLE 24-14: EXAMPLE SPI™ MODE REQUIREMENTS (CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
20
—
—
—
—
ns
73
TDIV2SCH, Setup Time of SDIx Data Input to SCKx Edge
TDIV2SCL
ns
73A
74
TB2B
Last Clock Edge of Byte 1 to the 1st Clock Edge 1.5 TCY + 40
of Byte 2
ns (Note 1)
TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
40
ns
75
76
78
79
80
TDOR
TDOF
TSCR
TSCF
SDOx Data Output Rise Time
—
—
—
—
—
25
25
25
25
50
ns
ns
ns
ns
ns
SDOx Data Output Fall Time
SCKx Output Rise Time (Master mode)
SCKx Output Fall Time (Master mode)
TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
Note 1: Only if Parameter #71A and #72A are used.
© 2009 Microchip Technology Inc.
DS39682E-page 325
MICROCHIP [ MICROCHIP ]
